130 	uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);  in fiji_is_smc_ram_running()
133 	return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C)));  in fiji_is_smc_ram_running()
248 		val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
349 	uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
353 	val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
548 		if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28) & fw_mask))  in fiji_smu_check_fw_load_finish()
568 	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);  in fiji_smu_start_in_protection_mode()
580 	val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);  in fiji_smu_start_in_protection_mode()
585 	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);  in fiji_smu_start_in_protection_mode()
590 	val = RREG32_SMC(ixSMU_INPUT_DATA);  in fiji_smu_start_in_protection_mode()
598 		val = RREG32_SMC(ixRCU_UC_EVENTS);  in fiji_smu_start_in_protection_mode()
616 		val = RREG32_SMC(ixSMU_STATUS);  in fiji_smu_start_in_protection_mode()
628 	val = RREG32_SMC(ixSMU_STATUS);  in fiji_smu_start_in_protection_mode()
636 		val = RREG32_SMC(ixFIRMWARE_FLAGS);  in fiji_smu_start_in_protection_mode()
658 		val = RREG32_SMC(ixRCU_UC_EVENTS);  in fiji_smu_start_in_non_protection_mode()
674 	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);  in fiji_smu_start_in_non_protection_mode()
686 	val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);  in fiji_smu_start_in_non_protection_mode()
691 	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);  in fiji_smu_start_in_non_protection_mode()
697 		val = RREG32_SMC(ixFIRMWARE_FLAGS);  in fiji_smu_start_in_non_protection_mode()
717 		val = RREG32_SMC(ixSMU_FIRMWARE);  in fiji_smu_start()