Lines Matching refs:pi
384 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi() local
386 return pi; in kv_get_pi()
466 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt() local
469 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
478 if (pi->caps_db_ramping) { in kv_do_enable_didt()
487 if (pi->caps_td_ramping) { in kv_do_enable_didt()
496 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
508 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt() local
511 if (pi->caps_sq_ramping || in kv_enable_didt()
512 pi->caps_db_ramping || in kv_enable_didt()
513 pi->caps_td_ramping || in kv_enable_didt()
514 pi->caps_tcp_ramping) { in kv_enable_didt()
536 struct kv_power_info *pi = kv_get_pi(adev);
538 if (pi->caps_cac) {
568 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_smc_cac() local
571 if (pi->caps_cac) { in kv_enable_smc_cac()
575 pi->cac_enabled = false; in kv_enable_smc_cac()
577 pi->cac_enabled = true; in kv_enable_smc_cac()
578 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
580 pi->cac_enabled = false; in kv_enable_smc_cac()
589 struct kv_power_info *pi = kv_get_pi(adev); in kv_process_firmware_header() local
595 &tmp, pi->sram_end); in kv_process_firmware_header()
598 pi->dpm_table_start = tmp; in kv_process_firmware_header()
602 &tmp, pi->sram_end); in kv_process_firmware_header()
605 pi->soft_regs_start = tmp; in kv_process_firmware_header()
612 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_dpm_voltage_scaling() local
615 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
618 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
620 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
621 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
628 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_interval() local
631 pi->graphics_interval = 1; in kv_set_dpm_interval()
634 pi->dpm_table_start + in kv_set_dpm_interval()
636 &pi->graphics_interval, in kv_set_dpm_interval()
637 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
644 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_boot_state() local
648 pi->dpm_table_start + in kv_set_dpm_boot_state()
650 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
651 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
669 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_divider_value() local
678 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
679 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
693 struct kv_power_info *pi = kv_get_pi(adev); in kv_convert_2bit_index_to_voltage() local
695 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
704 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_vid() local
706 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
707 pi->graphics_level[index].MinVddNb = in kv_set_vid()
715 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_at() local
717 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
725 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enable() local
727 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
787 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_sclk_t() local
791 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
792 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
795 pi->dpm_table_start + in kv_update_sclk_t()
798 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
805 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_bootup_state() local
811 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
812 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
816 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
820 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
825 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
826 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
830 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
838 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_auto_thermal_throttling() local
841 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
844 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
846 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
847 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
854 struct kv_power_info *pi = kv_get_pi(adev); in kv_upload_dpm_settings() local
858 pi->dpm_table_start + in kv_upload_dpm_settings()
860 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
862 pi->sram_end); in kv_upload_dpm_settings()
868 pi->dpm_table_start + in kv_upload_dpm_settings()
870 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
871 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
883 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_clk_bypass() local
886 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
908 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_uvd_table() local
918 pi->uvd_level_count = 0; in kv_populate_uvd_table()
920 if (pi->high_voltage_t && in kv_populate_uvd_table()
921 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
924 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
925 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
926 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
928 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
930 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
937 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
943 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
945 pi->uvd_level_count++; in kv_populate_uvd_table()
949 pi->dpm_table_start + in kv_populate_uvd_table()
951 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
952 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
956 pi->uvd_interval = 1; in kv_populate_uvd_table()
959 pi->dpm_table_start + in kv_populate_uvd_table()
961 &pi->uvd_interval, in kv_populate_uvd_table()
962 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
967 pi->dpm_table_start + in kv_populate_uvd_table()
969 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
971 pi->sram_end); in kv_populate_uvd_table()
979 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_vce_table() local
989 pi->vce_level_count = 0; in kv_populate_vce_table()
991 if (pi->high_voltage_t && in kv_populate_vce_table()
992 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
995 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
996 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
998 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
1005 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
1007 pi->vce_level_count++; in kv_populate_vce_table()
1011 pi->dpm_table_start + in kv_populate_vce_table()
1013 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
1015 pi->sram_end); in kv_populate_vce_table()
1019 pi->vce_interval = 1; in kv_populate_vce_table()
1022 pi->dpm_table_start + in kv_populate_vce_table()
1024 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
1026 pi->sram_end); in kv_populate_vce_table()
1031 pi->dpm_table_start + in kv_populate_vce_table()
1033 (u8 *)&pi->vce_level, in kv_populate_vce_table()
1035 pi->sram_end); in kv_populate_vce_table()
1042 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_samu_table() local
1052 pi->samu_level_count = 0; in kv_populate_samu_table()
1054 if (pi->high_voltage_t && in kv_populate_samu_table()
1055 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
1058 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
1059 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
1061 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
1068 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1070 pi->samu_level_count++; in kv_populate_samu_table()
1074 pi->dpm_table_start + in kv_populate_samu_table()
1076 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
1078 pi->sram_end); in kv_populate_samu_table()
1082 pi->samu_interval = 1; in kv_populate_samu_table()
1085 pi->dpm_table_start + in kv_populate_samu_table()
1087 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
1089 pi->sram_end); in kv_populate_samu_table()
1094 pi->dpm_table_start + in kv_populate_samu_table()
1096 (u8 *)&pi->samu_level, in kv_populate_samu_table()
1098 pi->sram_end); in kv_populate_samu_table()
1108 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_acp_table() local
1118 pi->acp_level_count = 0; in kv_populate_acp_table()
1120 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
1121 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
1127 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1129 pi->acp_level_count++; in kv_populate_acp_table()
1133 pi->dpm_table_start + in kv_populate_acp_table()
1135 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
1137 pi->sram_end); in kv_populate_acp_table()
1141 pi->acp_interval = 1; in kv_populate_acp_table()
1144 pi->dpm_table_start + in kv_populate_acp_table()
1146 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
1148 pi->sram_end); in kv_populate_acp_table()
1153 pi->dpm_table_start + in kv_populate_acp_table()
1155 (u8 *)&pi->acp_level, in kv_populate_acp_table()
1157 pi->sram_end); in kv_populate_acp_table()
1166 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dfs_bypass_settings() local
1172 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1173 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1175 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1177 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1179 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1181 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1183 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1185 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1187 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1192 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
1193 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1194 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1196 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1198 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1200 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1202 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1204 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1206 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1208 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1222 struct kv_power_info *pi = kv_get_pi(adev); in kv_reset_acp_boot_level() local
1224 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
1231 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_current_ps() local
1233 pi->current_rps = *rps; in kv_update_current_ps()
1234 pi->current_ps = *new_ps; in kv_update_current_ps()
1235 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
1242 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_requested_ps() local
1244 pi->requested_rps = *rps; in kv_update_requested_ps()
1245 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1246 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1251 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable_bapm() local
1254 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1263 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable() local
1309 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1406 struct kv_power_info *pi = kv_get_pi(adev);
1408 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1409 (u8 *)&value, sizeof(u16), pi->sram_end);
1415 struct kv_power_info *pi = kv_get_pi(adev);
1417 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1418 value, pi->sram_end);
1424 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_sclk_t() local
1426 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1431 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_fps_limits() local
1434 if (pi->caps_fps) { in kv_init_fps_limits()
1438 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1440 pi->dpm_table_start + in kv_init_fps_limits()
1442 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1443 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1446 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1449 pi->dpm_table_start + in kv_init_fps_limits()
1451 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1452 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1460 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_powergate_state() local
1462 pi->uvd_power_gated = false; in kv_init_powergate_state()
1463 pi->vce_power_gated = false; in kv_init_powergate_state()
1464 pi->samu_power_gated = false; in kv_init_powergate_state()
1465 pi->acp_power_gated = false; in kv_init_powergate_state()
1495 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_uvd_dpm() local
1503 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1505 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1507 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1508 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1514 pi->dpm_table_start + in kv_update_uvd_dpm()
1516 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1517 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1547 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_vce_dpm() local
1559 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1560 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1562 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1565 pi->dpm_table_start + in kv_update_vce_dpm()
1567 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1569 pi->sram_end); in kv_update_vce_dpm()
1573 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1576 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1594 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_samu_dpm() local
1600 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1601 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1603 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1606 pi->dpm_table_start + in kv_update_samu_dpm()
1608 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1610 pi->sram_end); in kv_update_samu_dpm()
1614 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1617 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1642 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_boot_level() local
1645 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1647 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1648 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1651 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1658 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_dpm() local
1664 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1665 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1667 pi->acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_dpm()
1670 pi->dpm_table_start + in kv_update_acp_dpm()
1672 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1674 pi->sram_end); in kv_update_acp_dpm()
1678 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1681 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1689 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_uvd() local
1692 if (pi->uvd_power_gated == gate) in kv_dpm_powergate_uvd()
1695 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1698 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1708 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1712 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1729 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_vce() local
1732 if (pi->vce_power_gated == gate) in kv_dpm_powergate_vce()
1735 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1738 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1747 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1760 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_samu() local
1762 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1765 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1769 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1772 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1780 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_acp() local
1782 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1788 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1792 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1795 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1805 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_valid_clock_range() local
1811 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1813 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1814 pi->lowest_valid = i; in kv_set_valid_clock_range()
1819 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1823 pi->highest_valid = i; in kv_set_valid_clock_range()
1825 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1826 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1827 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1828 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1830 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1834 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1836 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1838 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1839 pi->lowest_valid = i; in kv_set_valid_clock_range()
1844 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1849 pi->highest_valid = i; in kv_set_valid_clock_range()
1851 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1853 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1854 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1856 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1858 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1867 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_dfs_bypass_settings() local
1871 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1873 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1875 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1877 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1880 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1889 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_nb_dpm() local
1893 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1896 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1899 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1902 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1935 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_pre_set_power_state() local
1942 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1943 &pi->current_rps); in kv_dpm_pre_set_power_state()
1950 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_set_power_state() local
1951 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1952 struct amdgpu_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1955 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1964 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1993 if (pi->enable_dpm) { in kv_dpm_set_power_state()
2024 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_post_set_power_state() local
2025 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
2040 struct kv_power_info *pi = kv_get_pi(adev);
2055 kv_set_enabled_level(adev, pi->graphics_boot_level);
2063 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_max_power_limits_table() local
2065 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
2066 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
2068 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
2071 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
2074 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
2121 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_boot_state() local
2123 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
2124 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
2125 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
2126 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
2127 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
2128 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
2129 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
2130 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
2176 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_sleep_divider_id_from_clock() local
2185 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
2199 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_high_voltage_limit() local
2206 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2208 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2215 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
2218 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2220 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2236 struct kv_power_info *pi = kv_get_pi(adev); in kv_apply_state_adjust_rules() local
2258 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2288 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2289 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2297 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2300 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2301 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2309 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2315 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2320 pi->battery_state = true; in kv_apply_state_adjust_rules()
2322 pi->battery_state = false; in kv_apply_state_adjust_rules()
2335 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2336 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2337 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2338 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2350 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enabled_for_throttle() local
2352 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2357 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_ds_divider() local
2361 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2364 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2365 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2367 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2375 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_nbps_level_settings() local
2382 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2386 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2387 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2388 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2389 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2392 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2395 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2396 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2399 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2400 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2402 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2403 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2405 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2406 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2407 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2408 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2411 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2412 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2413 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2414 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2417 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2418 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2419 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2420 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2421 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2429 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dpm_settings() local
2432 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2435 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2436 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2443 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_graphics_levels() local
2451 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2453 if (pi->high_voltage_t && in kv_init_graphics_levels()
2454 (pi->high_voltage_t < in kv_init_graphics_levels()
2460 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2463 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2465 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2469 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2471 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2473 if (pi->high_voltage_t && in kv_init_graphics_levels()
2474 pi->high_voltage_t < in kv_init_graphics_levels()
2480 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2482 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2492 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_new_levels() local
2496 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2512 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_enabled_levels() local
2515 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2527 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_nbps_index_settings() local
2533 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2587 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_sys_info_table() local
2604 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2605 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2606 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2609 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2611 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2613 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2615 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2616 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2621 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2623 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2626 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2628 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2633 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2636 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2640 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2673 struct kv_power_info *pi = kv_get_pi(adev); in kv_patch_boot_state() local
2676 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2710 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_pplib_clock_info() local
2722 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2819 struct kv_power_info *pi; in kv_dpm_init() local
2822 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2823 if (pi == NULL) in kv_dpm_init()
2825 adev->pm.dpm.priv = pi; in kv_dpm_init()
2836 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2838 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2840 pi->enable_nb_dpm = true; in kv_dpm_init()
2842 pi->caps_power_containment = true; in kv_dpm_init()
2843 pi->caps_cac = true; in kv_dpm_init()
2844 pi->enable_didt = false; in kv_dpm_init()
2845 if (pi->enable_didt) { in kv_dpm_init()
2846 pi->caps_sq_ramping = true; in kv_dpm_init()
2847 pi->caps_db_ramping = true; in kv_dpm_init()
2848 pi->caps_td_ramping = true; in kv_dpm_init()
2849 pi->caps_tcp_ramping = true; in kv_dpm_init()
2852 pi->caps_sclk_ds = true; in kv_dpm_init()
2853 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2854 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2856 pi->bapm_enable = false; in kv_dpm_init()
2858 pi->bapm_enable = true; in kv_dpm_init()
2859 pi->voltage_drop_t = 0; in kv_dpm_init()
2860 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2861 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2862 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; in kv_dpm_init()
2863 pi->caps_uvd_dpm = true; in kv_dpm_init()
2864 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; in kv_dpm_init()
2865 pi->caps_samu_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_SAMU) ? true : false; in kv_dpm_init()
2866 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; in kv_dpm_init()
2867 pi->caps_stable_p_state = false; in kv_dpm_init()
2880 pi->enable_dpm = true; in kv_dpm_init()
2889 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_debugfs_print_current_performance_level() local
2900 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2905 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2906 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2950 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_sclk() local
2951 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2961 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_mclk() local
2963 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()