251 	addrHi->u32All = 0;  in dbgdev_address_watch_set_registers()
252 	addrLo->u32All = 0;  in dbgdev_address_watch_set_registers()
253 	cntl->u32All = 0;  in dbgdev_address_watch_set_registers()
272 	cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT;  in dbgdev_address_watch_set_registers()
300 	addrHi.u32All = 0;  in dbgdev_address_watch_nodiq()
301 	addrLo.u32All = 0;  in dbgdev_address_watch_nodiq()
302 	cntl.u32All = 0;  in dbgdev_address_watch_nodiq()
342 						cntl.u32All,  in dbgdev_address_watch_nodiq()
343 						addrHi.u32All,  in dbgdev_address_watch_nodiq()
344 						addrLo.u32All);  in dbgdev_address_watch_nodiq()
368 	addrHi.u32All = 0;  in dbgdev_address_watch_diq()
369 	addrLo.u32All = 0;  in dbgdev_address_watch_diq()
370 	cntl.u32All = 0;  in dbgdev_address_watch_diq()
450 		packets_vec[0].reg_data[0] = cntl.u32All;  in dbgdev_address_watch_diq()
462 		packets_vec[1].reg_data[0] = addrHi.u32All;  in dbgdev_address_watch_diq()
474 		packets_vec[2].reg_data[0] = addrLo.u32All;  in dbgdev_address_watch_diq()
492 		packets_vec[3].reg_data[0] = cntl.u32All;  in dbgdev_address_watch_diq()
523 	reg_sq_cmd.u32All = 0;  in dbgdev_wave_control_set_registers()
524 	reg_gfx_index.u32All = 0;  in dbgdev_wave_control_set_registers()
625 	reg_sq_cmd.u32All = 0;  in dbgdev_wave_control_diq()
687 	packets_vec[0].reg_data[0] = reg_gfx_index.u32All;  in dbgdev_wave_control_diq()
697 	packets_vec[1].reg_data[0] = reg_sq_cmd.u32All;  in dbgdev_wave_control_diq()
701 	reg_gfx_index.u32All = 0;  in dbgdev_wave_control_diq()
713 	packets_vec[2].reg_data[0] = reg_gfx_index.u32All;  in dbgdev_wave_control_diq()
740 	reg_sq_cmd.u32All = 0;  in dbgdev_wave_control_nodiq()
791 							reg_gfx_index.u32All,  in dbgdev_wave_control_nodiq()
792 							reg_sq_cmd.u32All);  in dbgdev_wave_control_nodiq()
811 	reg_sq_cmd.u32All = 0;  in dbgdev_wave_reset_wavefronts()
854 					reg_gfx_index.u32All,  in dbgdev_wave_reset_wavefronts()
855 					reg_sq_cmd.u32All);  in dbgdev_wave_reset_wavefronts()