257 	uint32_t output_reg;  member
573 	uint32_t output_reg = intel_dp->output_reg;  in cdv_intel_dp_aux_ch()  local
575 	uint32_t ch_ctl = output_reg + 0x10;  in cdv_intel_dp_aux_ch()
1088 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));  in cdv_intel_dp_mode_set()
1174 	uint32_t dp_reg = REG_READ(intel_dp->output_reg);  in cdv_intel_dp_dpms()
1393 	REG_WRITE(intel_dp->output_reg, dp_reg_value);  in cdv_intel_dp_set_link_train()
1394 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_set_link_train()
1439 	if (intel_dp->output_reg == DP_B)  in cdv_intel_dp_set_vswing_premph()
1515 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_start_link_train()
1516 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_start_link_train()
1671 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_complete_link_train()
1672 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_complete_link_train()
1684 	if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)  in cdv_intel_dp_link_down()
1692 		REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);  in cdv_intel_dp_link_down()
1694 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_link_down()
1698 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in cdv_intel_dp_link_down()
1699 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_link_down()
1996 cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)  in cdv_intel_dp_init()  argument
2016 	if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev))  in cdv_intel_dp_init()
2035 	intel_dp->output_reg = output_reg;  in cdv_intel_dp_init()
2047 	switch (output_reg) {  in cdv_intel_dp_init()