Lines Matching refs:reg_write
476 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) in reg_write() function
520 reg_write(priv, reg, old_val | val); in reg_set()
530 reg_write(priv, reg, old_val & ~val); in reg_clear()
537 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); in tda998x_reset()
539 reg_write(priv, REG_SOFTRESET, 0); in tda998x_reset()
547 reg_write(priv, REG_PLL_SERIAL_1, 0x00); in tda998x_reset()
548 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); in tda998x_reset()
549 reg_write(priv, REG_PLL_SERIAL_3, 0x00); in tda998x_reset()
550 reg_write(priv, REG_SERIALIZER, 0x00); in tda998x_reset()
551 reg_write(priv, REG_BUFFER_OUT, 0x00); in tda998x_reset()
552 reg_write(priv, REG_PLL_SCG1, 0x00); in tda998x_reset()
553 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); in tda998x_reset()
554 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); in tda998x_reset()
555 reg_write(priv, REG_PLL_SCGN1, 0xfa); in tda998x_reset()
556 reg_write(priv, REG_PLL_SCGN2, 0x00); in tda998x_reset()
557 reg_write(priv, REG_PLL_SCGR1, 0x5b); in tda998x_reset()
558 reg_write(priv, REG_PLL_SCGR2, 0x00); in tda998x_reset()
559 reg_write(priv, REG_PLL_SCG2, 0x10); in tda998x_reset()
562 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); in tda998x_reset()
720 reg_write(priv, REG_ENA_AP, p->audio_cfg); in tda998x_configure_audio()
721 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg); in tda998x_configure_audio()
726 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF); in tda998x_configure_audio()
733 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S); in tda998x_configure_audio()
744 reg_write(priv, REG_AIP_CLKSEL, clksel_aip); in tda998x_configure_audio()
747 reg_write(priv, REG_CTS_N, cts_n); in tda998x_configure_audio()
764 reg_write(priv, REG_AUDIO_DIV, adiv); in tda998x_configure_audio()
782 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs); in tda998x_configure_audio()
839 reg_write(priv, REG_ENA_VP_0, 0xff); in tda998x_encoder_dpms()
840 reg_write(priv, REG_ENA_VP_1, 0xff); in tda998x_encoder_dpms()
841 reg_write(priv, REG_ENA_VP_2, 0xff); in tda998x_encoder_dpms()
843 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); in tda998x_encoder_dpms()
844 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); in tda998x_encoder_dpms()
845 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); in tda998x_encoder_dpms()
849 reg_write(priv, REG_ENA_VP_0, 0x00); in tda998x_encoder_dpms()
850 reg_write(priv, REG_ENA_VP_1, 0x00); in tda998x_encoder_dpms()
851 reg_write(priv, REG_ENA_VP_2, 0x00); in tda998x_encoder_dpms()
977 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); in tda998x_encoder_mode_set()
979 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); in tda998x_encoder_mode_set()
982 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | in tda998x_encoder_mode_set()
984 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); in tda998x_encoder_mode_set()
985 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | in tda998x_encoder_mode_set()
991 reg_write(priv, REG_SERIALIZER, 0); in tda998x_encoder_mode_set()
992 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); in tda998x_encoder_mode_set()
996 reg_write(priv, REG_RPT_CNTRL, 0); in tda998x_encoder_mode_set()
997 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | in tda998x_encoder_mode_set()
1000 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | in tda998x_encoder_mode_set()
1004 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | in tda998x_encoder_mode_set()
1008 reg_write(priv, REG_ANA_GENERAL, 0x09); in tda998x_encoder_mode_set()
1023 reg_write(priv, REG_VIP_CNTRL_3, reg); in tda998x_encoder_mode_set()
1025 reg_write(priv, REG_VIDFORMAT, 0x00); in tda998x_encoder_mode_set()
1049 reg_write(priv, REG_ENABLE_SPACE, 0x00); in tda998x_encoder_mode_set()
1061 reg_write(priv, REG_TBG_CNTRL_1, reg); in tda998x_encoder_mode_set()
1064 reg_write(priv, REG_TBG_CNTRL_0, 0); in tda998x_encoder_mode_set()
1070 reg_write(priv, REG_TBG_CNTRL_1, reg); in tda998x_encoder_mode_set()
1071 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); in tda998x_encoder_mode_set()
1101 reg_write(priv, REG_DDC_ADDR, 0xa0); in read_edid_block()
1102 reg_write(priv, REG_DDC_OFFS, offset); in read_edid_block()
1103 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); in read_edid_block()
1104 reg_write(priv, REG_DDC_SEGM, segptr); in read_edid_block()
1108 reg_write(priv, REG_EDID_CTRL, 0x1); in read_edid_block()
1111 reg_write(priv, REG_EDID_CTRL, 0x0); in read_edid_block()
1276 reg_write(priv, REG_DDC_DISABLE, 0x00); in tda998x_create()
1279 reg_write(priv, REG_TX3, 39); in tda998x_create()