Lines Matching refs:pipe
477 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_enable_pipestat() argument
480 u32 reg = PIPESTAT(pipe); in __i915_enable_pipestat()
489 pipe_name(pipe), enable_mask, status_mask)) in __i915_enable_pipestat()
495 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in __i915_enable_pipestat()
504 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_disable_pipestat() argument
507 u32 reg = PIPESTAT(pipe); in __i915_disable_pipestat()
516 pipe_name(pipe), enable_mask, status_mask)) in __i915_disable_pipestat()
522 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in __i915_disable_pipestat()
558 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_enable_pipestat() argument
568 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_enable_pipestat()
572 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_disable_pipestat() argument
582 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_disable_pipestat()
656 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe) in i8xx_get_vblank_counter() argument
665 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) in i915_get_vblank_counter() argument
672 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in i915_get_vblank_counter()
687 high_frame = PIPEFRAME(pipe); in i915_get_vblank_counter()
688 low_frame = PIPEFRAMEPIXEL(pipe); in i915_get_vblank_counter()
713 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) in g4x_get_vblank_counter() argument
717 return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); in g4x_get_vblank_counter()
728 enum pipe pipe = crtc->pipe; in __intel_get_crtc_scanline() local
736 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; in __intel_get_crtc_scanline()
738 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()
757 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & in __intel_get_crtc_scanline()
773 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, in i915_get_crtc_scanoutpos() argument
779 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in i915_get_crtc_scanoutpos()
789 "pipe %c\n", pipe_name(pipe)); in i915_get_crtc_scanoutpos()
830 …position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHI… in i915_get_crtc_scanoutpos()
910 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, in i915_get_vblank_timestamp() argument
917 if (pipe >= INTEL_INFO(dev)->num_pipes) { in i915_get_vblank_timestamp()
918 DRM_ERROR("Invalid crtc %u\n", pipe); in i915_get_vblank_timestamp()
923 crtc = intel_get_crtc_for_pipe(dev, pipe); in i915_get_vblank_timestamp()
925 DRM_ERROR("Invalid crtc %u\n", pipe); in i915_get_vblank_timestamp()
930 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe); in i915_get_vblank_timestamp()
935 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, in i915_get_vblank_timestamp()
1473 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, in display_pipe_crc_irq_handler() argument
1479 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; in display_pipe_crc_irq_handler()
1502 entry->frame = dev->driver->get_vblank_counter(dev, pipe); in display_pipe_crc_irq_handler()
1518 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, in display_pipe_crc_irq_handler() argument
1525 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) in hsw_pipe_crc_irq_handler() argument
1529 display_pipe_crc_irq_handler(dev, pipe, in hsw_pipe_crc_irq_handler()
1530 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), in hsw_pipe_crc_irq_handler()
1534 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) in ivb_pipe_crc_irq_handler() argument
1538 display_pipe_crc_irq_handler(dev, pipe, in ivb_pipe_crc_irq_handler()
1539 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1540 I915_READ(PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1541 I915_READ(PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1542 I915_READ(PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1543 I915_READ(PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
1546 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) in i9xx_pipe_crc_irq_handler() argument
1552 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); in i9xx_pipe_crc_irq_handler()
1557 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); in i9xx_pipe_crc_irq_handler()
1561 display_pipe_crc_irq_handler(dev, pipe, in i9xx_pipe_crc_irq_handler()
1562 I915_READ(PIPE_CRC_RES_RED(pipe)), in i9xx_pipe_crc_irq_handler()
1563 I915_READ(PIPE_CRC_RES_GREEN(pipe)), in i9xx_pipe_crc_irq_handler()
1564 I915_READ(PIPE_CRC_RES_BLUE(pipe)), in i9xx_pipe_crc_irq_handler()
1595 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) in intel_pipe_handle_vblank() argument
1597 if (!drm_handle_vblank(dev, pipe)) in intel_pipe_handle_vblank()
1607 int pipe; in valleyview_pipestat_irq_handler() local
1610 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1625 switch (pipe) { in valleyview_pipestat_irq_handler()
1637 mask |= dev_priv->pipestat_irq_mask[pipe]; in valleyview_pipestat_irq_handler()
1642 reg = PIPESTAT(pipe); in valleyview_pipestat_irq_handler()
1644 pipe_stats[pipe] = I915_READ(reg) & mask; in valleyview_pipestat_irq_handler()
1649 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | in valleyview_pipestat_irq_handler()
1651 I915_WRITE(reg, pipe_stats[pipe]); in valleyview_pipestat_irq_handler()
1655 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1656 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && in valleyview_pipestat_irq_handler()
1657 intel_pipe_handle_vblank(dev, pipe)) in valleyview_pipestat_irq_handler()
1658 intel_check_page_flip(dev, pipe); in valleyview_pipestat_irq_handler()
1660 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { in valleyview_pipestat_irq_handler()
1661 intel_prepare_page_flip(dev, pipe); in valleyview_pipestat_irq_handler()
1662 intel_finish_page_flip(dev, pipe); in valleyview_pipestat_irq_handler()
1665 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
1666 i9xx_pipe_crc_irq_handler(dev, pipe); in valleyview_pipestat_irq_handler()
1668 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in valleyview_pipestat_irq_handler()
1669 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
1826 int pipe; in ibx_irq_handler() local
1855 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
1857 pipe_name(pipe), in ibx_irq_handler()
1858 I915_READ(FDI_RX_IIR(pipe))); in ibx_irq_handler()
1877 enum pipe pipe; in ivb_err_int_handler() local
1882 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
1883 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) in ivb_err_int_handler()
1884 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
1886 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { in ivb_err_int_handler()
1888 ivb_pipe_crc_irq_handler(dev, pipe); in ivb_err_int_handler()
1890 hsw_pipe_crc_irq_handler(dev, pipe); in ivb_err_int_handler()
1920 int pipe; in cpt_irq_handler() local
1946 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
1948 pipe_name(pipe), in cpt_irq_handler()
1949 I915_READ(FDI_RX_IIR(pipe))); in cpt_irq_handler()
2011 enum pipe pipe; in ilk_display_irq_handler() local
2026 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
2027 if (de_iir & DE_PIPE_VBLANK(pipe) && in ilk_display_irq_handler()
2028 intel_pipe_handle_vblank(dev, pipe)) in ilk_display_irq_handler()
2029 intel_check_page_flip(dev, pipe); in ilk_display_irq_handler()
2031 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) in ilk_display_irq_handler()
2032 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
2034 if (de_iir & DE_PIPE_CRC_DONE(pipe)) in ilk_display_irq_handler()
2035 i9xx_pipe_crc_irq_handler(dev, pipe); in ilk_display_irq_handler()
2038 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { in ilk_display_irq_handler()
2039 intel_prepare_page_flip(dev, pipe); in ilk_display_irq_handler()
2040 intel_finish_page_flip_plane(dev, pipe); in ilk_display_irq_handler()
2064 enum pipe pipe; in ivb_display_irq_handler() local
2079 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
2080 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && in ivb_display_irq_handler()
2081 intel_pipe_handle_vblank(dev, pipe)) in ivb_display_irq_handler()
2082 intel_check_page_flip(dev, pipe); in ivb_display_irq_handler()
2085 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { in ivb_display_irq_handler()
2086 intel_prepare_page_flip(dev, pipe); in ivb_display_irq_handler()
2087 intel_finish_page_flip_plane(dev, pipe); in ivb_display_irq_handler()
2204 enum pipe pipe; in gen8_irq_handler() local
2278 for_each_pipe(dev_priv, pipe) { in gen8_irq_handler()
2281 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) in gen8_irq_handler()
2284 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); in gen8_irq_handler()
2287 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); in gen8_irq_handler()
2290 intel_pipe_handle_vblank(dev, pipe)) in gen8_irq_handler()
2291 intel_check_page_flip(dev, pipe); in gen8_irq_handler()
2299 intel_prepare_page_flip(dev, pipe); in gen8_irq_handler()
2300 intel_finish_page_flip_plane(dev, pipe); in gen8_irq_handler()
2304 hsw_pipe_crc_irq_handler(dev, pipe); in gen8_irq_handler()
2308 pipe); in gen8_irq_handler()
2318 pipe_name(pipe), in gen8_irq_handler()
2472 int pipe, i; in i915_report_and_clear_eir() local
2515 for_each_pipe(dev_priv, pipe) in i915_report_and_clear_eir()
2517 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); in i915_report_and_clear_eir()
2609 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) in i915_enable_vblank() argument
2616 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2619 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2626 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) in ironlake_enable_vblank() argument
2630 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : in ironlake_enable_vblank()
2631 DE_PIPE_VBLANK(pipe); in ironlake_enable_vblank()
2640 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe) in valleyview_enable_vblank() argument
2646 i915_enable_pipestat(dev_priv, pipe, in valleyview_enable_vblank()
2653 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) in gen8_enable_vblank() argument
2659 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; in gen8_enable_vblank()
2660 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_enable_vblank()
2661 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in gen8_enable_vblank()
2669 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe) in i915_disable_vblank() argument
2675 i915_disable_pipestat(dev_priv, pipe, in i915_disable_vblank()
2681 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) in ironlake_disable_vblank() argument
2685 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : in ironlake_disable_vblank()
2686 DE_PIPE_VBLANK(pipe); in ironlake_disable_vblank()
2693 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe) in valleyview_disable_vblank() argument
2699 i915_disable_pipestat(dev_priv, pipe, in valleyview_disable_vblank()
2704 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) in gen8_disable_vblank() argument
2710 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; in gen8_disable_vblank()
2711 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_disable_vblank()
2712 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in gen8_disable_vblank()
3128 enum pipe pipe; in vlv_display_irq_reset() local
3133 for_each_pipe(dev_priv, pipe) in vlv_display_irq_reset()
3134 I915_WRITE(PIPESTAT(pipe), 0xffff); in vlv_display_irq_reset()
3167 int pipe; in gen8_irq_reset() local
3174 for_each_pipe(dev_priv, pipe) in gen8_irq_reset()
3176 POWER_DOMAIN_PIPE(pipe))) in gen8_irq_reset()
3177 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); in gen8_irq_reset()
3452 enum pipe pipe; in valleyview_display_irqs_install() local
3457 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3458 I915_WRITE(PIPESTAT(pipe), pipestat_mask); in valleyview_display_irqs_install()
3465 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3466 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_install()
3486 enum pipe pipe; in valleyview_display_irqs_uninstall() local
3505 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3506 i915_disable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_uninstall()
3511 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3512 I915_WRITE(PIPESTAT(pipe), pipestat_mask); in valleyview_display_irqs_uninstall()
3617 enum pipe pipe; in gen8_de_irq_postinstall() local
3644 for_each_pipe(dev_priv, pipe) in gen8_de_irq_postinstall()
3646 POWER_DOMAIN_PIPE(pipe))) in gen8_de_irq_postinstall()
3647 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, in gen8_de_irq_postinstall()
3648 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()
3757 int pipe; in i8xx_irq_preinstall() local
3759 for_each_pipe(dev_priv, pipe) in i8xx_irq_preinstall()
3760 I915_WRITE(PIPESTAT(pipe), 0); in i8xx_irq_preinstall()
3801 int plane, int pipe, u32 iir) in i8xx_handle_vblank() argument
3806 if (!intel_pipe_handle_vblank(dev, pipe)) in i8xx_handle_vblank()
3822 intel_finish_page_flip(dev, pipe); in i8xx_handle_vblank()
3826 intel_check_page_flip(dev, pipe); in i8xx_handle_vblank()
3836 int pipe; in i8xx_irq_handler() local
3858 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3859 int reg = PIPESTAT(pipe); in i8xx_irq_handler()
3860 pipe_stats[pipe] = I915_READ(reg); in i8xx_irq_handler()
3865 if (pipe_stats[pipe] & 0x8000ffff) in i8xx_irq_handler()
3866 I915_WRITE(reg, pipe_stats[pipe]); in i8xx_irq_handler()
3876 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3877 int plane = pipe; in i8xx_irq_handler()
3881 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && in i8xx_irq_handler()
3882 i8xx_handle_vblank(dev, plane, pipe, iir)) in i8xx_irq_handler()
3885 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i8xx_irq_handler()
3886 i9xx_pipe_crc_irq_handler(dev, pipe); in i8xx_irq_handler()
3888 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i8xx_irq_handler()
3890 pipe); in i8xx_irq_handler()
3902 int pipe; in i8xx_irq_uninstall() local
3904 for_each_pipe(dev_priv, pipe) { in i8xx_irq_uninstall()
3906 I915_WRITE(PIPESTAT(pipe), 0); in i8xx_irq_uninstall()
3907 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); in i8xx_irq_uninstall()
3917 int pipe; in i915_irq_preinstall() local
3925 for_each_pipe(dev_priv, pipe) in i915_irq_preinstall()
3926 I915_WRITE(PIPESTAT(pipe), 0); in i915_irq_preinstall()
3983 int plane, int pipe, u32 iir) in i915_handle_vblank() argument
3988 if (!intel_pipe_handle_vblank(dev, pipe)) in i915_handle_vblank()
4004 intel_finish_page_flip(dev, pipe); in i915_handle_vblank()
4008 intel_check_page_flip(dev, pipe); in i915_handle_vblank()
4020 int pipe, ret = IRQ_NONE; in i915_irq_handler() local
4039 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
4040 int reg = PIPESTAT(pipe); in i915_irq_handler()
4041 pipe_stats[pipe] = I915_READ(reg); in i915_irq_handler()
4044 if (pipe_stats[pipe] & 0x8000ffff) { in i915_irq_handler()
4045 I915_WRITE(reg, pipe_stats[pipe]); in i915_irq_handler()
4065 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
4066 int plane = pipe; in i915_irq_handler()
4070 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && in i915_irq_handler()
4071 i915_handle_vblank(dev, plane, pipe, iir)) in i915_irq_handler()
4074 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i915_irq_handler()
4077 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i915_irq_handler()
4078 i9xx_pipe_crc_irq_handler(dev, pipe); in i915_irq_handler()
4080 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i915_irq_handler()
4082 pipe); in i915_irq_handler()
4113 int pipe; in i915_irq_uninstall() local
4121 for_each_pipe(dev_priv, pipe) { in i915_irq_uninstall()
4123 I915_WRITE(PIPESTAT(pipe), 0); in i915_irq_uninstall()
4124 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); in i915_irq_uninstall()
4135 int pipe; in i965_irq_preinstall() local
4141 for_each_pipe(dev_priv, pipe) in i965_irq_preinstall()
4142 I915_WRITE(PIPESTAT(pipe), 0); in i965_irq_preinstall()
4238 int ret = IRQ_NONE, pipe; in i965_irq_handler() local
4261 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4262 int reg = PIPESTAT(pipe); in i965_irq_handler()
4263 pipe_stats[pipe] = I915_READ(reg); in i965_irq_handler()
4268 if (pipe_stats[pipe] & 0x8000ffff) { in i965_irq_handler()
4269 I915_WRITE(reg, pipe_stats[pipe]); in i965_irq_handler()
4292 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4293 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && in i965_irq_handler()
4294 i915_handle_vblank(dev, pipe, pipe, iir)) in i965_irq_handler()
4295 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); in i965_irq_handler()
4297 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i965_irq_handler()
4300 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i965_irq_handler()
4301 i9xx_pipe_crc_irq_handler(dev, pipe); in i965_irq_handler()
4303 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i965_irq_handler()
4304 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_irq_handler()
4337 int pipe; in i965_irq_uninstall() local
4346 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4347 I915_WRITE(PIPESTAT(pipe), 0); in i965_irq_uninstall()
4351 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4352 I915_WRITE(PIPESTAT(pipe), in i965_irq_uninstall()
4353 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); in i965_irq_uninstall()