281 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_act_freq_mhz_show()
285 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_act_freq_mhz_show()
300 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_act_freq_mhz_show()
315 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_cur_freq_mhz_show()
319 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_cur_freq_mhz_show()
320 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);  in gt_cur_freq_mhz_show()
321 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_cur_freq_mhz_show()
337 			intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));  in vlv_rpe_freq_mhz_show()
347 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_max_freq_mhz_show()
349 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_show()
350 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);  in gt_max_freq_mhz_show()
351 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_show()
370 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_max_freq_mhz_store()
372 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
376 	if (val < dev_priv->rps.min_freq ||  in gt_max_freq_mhz_store()
377 	    val > dev_priv->rps.max_freq ||  in gt_max_freq_mhz_store()
378 	    val < dev_priv->rps.min_freq_softlimit) {  in gt_max_freq_mhz_store()
379 		mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
383 	if (val > dev_priv->rps.rp0_freq)  in gt_max_freq_mhz_store()
387 	dev_priv->rps.max_freq_softlimit = val;  in gt_max_freq_mhz_store()
389 	val = clamp_t(int, dev_priv->rps.cur_freq,  in gt_max_freq_mhz_store()
390 		      dev_priv->rps.min_freq_softlimit,  in gt_max_freq_mhz_store()
391 		      dev_priv->rps.max_freq_softlimit);  in gt_max_freq_mhz_store()
398 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
410 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_min_freq_mhz_show()
412 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_show()
413 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);  in gt_min_freq_mhz_show()
414 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_show()
433 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_min_freq_mhz_store()
435 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
439 	if (val < dev_priv->rps.min_freq ||  in gt_min_freq_mhz_store()
440 	    val > dev_priv->rps.max_freq ||  in gt_min_freq_mhz_store()
441 	    val > dev_priv->rps.max_freq_softlimit) {  in gt_min_freq_mhz_store()
442 		mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
446 	dev_priv->rps.min_freq_softlimit = val;  in gt_min_freq_mhz_store()
448 	val = clamp_t(int, dev_priv->rps.cur_freq,  in gt_min_freq_mhz_store()
449 		      dev_priv->rps.min_freq_softlimit,  in gt_min_freq_mhz_store()
450 		      dev_priv->rps.max_freq_softlimit);  in gt_min_freq_mhz_store()
457 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
484 		val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);  in gt_rp_mhz_show()
486 		val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);  in gt_rp_mhz_show()
488 		val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);  in gt_rp_mhz_show()