Lines Matching refs:I915_WRITE
532 I915_WRITE(DDI_BUF_TRANS_LO(port, i), in intel_prepare_ddi_buffers()
534 I915_WRITE(DDI_BUF_TRANS_HI(port, i), in intel_prepare_ddi_buffers()
547 I915_WRITE(DDI_BUF_TRANS_LO(port, i), in intel_prepare_ddi_buffers()
549 I915_WRITE(DDI_BUF_TRANS_HI(port, i), in intel_prepare_ddi_buffers()
621 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
629 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
635 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
638 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); in hsw_fdi_link_train()
645 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
655 I915_WRITE(DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
664 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
668 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
677 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
688 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
699 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); in hsw_fdi_link_train()
706 I915_WRITE(DP_TP_CTL(PORT_E), temp); in hsw_fdi_link_train()
712 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
719 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
1830 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); in intel_ddi_set_pipe_settings()
1846 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); in intel_ddi_set_vc_payload_alloc()
1948 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); in intel_ddi_enable_transcoder_func()
1959 I915_WRITE(reg, val); in intel_ddi_disable_transcoder_func()
2076 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), in intel_ddi_enable_pipe_clock()
2086 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), in intel_ddi_disable_pipe_clock()
2144 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); in skl_ddi_set_iboost()
2188 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); in bxt_ddi_vswing_sequence()
2194 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); in bxt_ddi_vswing_sequence()
2204 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); in bxt_ddi_vswing_sequence()
2209 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); in bxt_ddi_vswing_sequence()
2213 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); in bxt_ddi_vswing_sequence()
2316 I915_WRITE(DPLL_CTRL1, val); in intel_ddi_pre_enable()
2328 I915_WRITE(DPLL_CTRL2, val); in intel_ddi_pre_enable()
2332 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); in intel_ddi_pre_enable()
2374 I915_WRITE(DDI_BUF_CTL(port), val); in intel_ddi_post_disable()
2381 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_post_disable()
2394 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | in intel_ddi_post_disable()
2397 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); in intel_ddi_post_disable()
2418 I915_WRITE(DDI_BUF_CTL(port), in intel_enable_ddi()
2464 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); in hsw_ddi_wrpll_enable()
2472 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); in hsw_ddi_spll_enable()
2483 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); in hsw_ddi_wrpll_disable()
2493 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); in hsw_ddi_spll_disable()
2606 I915_WRITE(DPLL_CTRL1, val); in skl_ddi_pll_enable()
2609 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); in skl_ddi_pll_enable()
2610 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); in skl_ddi_pll_enable()
2615 I915_WRITE(regs[pll->id].ctl, in skl_ddi_pll_enable()
2628 I915_WRITE(regs[pll->id].ctl, in skl_ddi_pll_disable()
2687 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); in broxton_phy_init()
2707 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); in broxton_phy_init()
2715 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); in broxton_phy_init()
2720 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); in broxton_phy_init()
2726 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); in broxton_phy_init()
2731 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); in broxton_phy_init()
2745 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); in broxton_phy_init()
2763 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); in broxton_phy_init()
2767 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); in broxton_phy_init()
2772 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); in broxton_phy_init()
2789 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); in broxton_phy_uninit()
2800 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); in broxton_ddi_phy_uninit()
2818 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); in bxt_ddi_pll_enable()
2823 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); in bxt_ddi_pll_enable()
2829 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); in bxt_ddi_pll_enable()
2835 I915_WRITE(BXT_PORT_PLL(port, 0), temp); in bxt_ddi_pll_enable()
2841 I915_WRITE(BXT_PORT_PLL(port, 1), temp); in bxt_ddi_pll_enable()
2847 I915_WRITE(BXT_PORT_PLL(port, 2), temp); in bxt_ddi_pll_enable()
2853 I915_WRITE(BXT_PORT_PLL(port, 3), temp); in bxt_ddi_pll_enable()
2861 I915_WRITE(BXT_PORT_PLL(port, 6), temp); in bxt_ddi_pll_enable()
2867 I915_WRITE(BXT_PORT_PLL(port, 8), temp); in bxt_ddi_pll_enable()
2872 I915_WRITE(BXT_PORT_PLL(port, 9), temp); in bxt_ddi_pll_enable()
2878 I915_WRITE(BXT_PORT_PLL(port, 10), temp); in bxt_ddi_pll_enable()
2883 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); in bxt_ddi_pll_enable()
2886 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); in bxt_ddi_pll_enable()
2891 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); in bxt_ddi_pll_enable()
2906 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); in bxt_ddi_pll_enable()
2917 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); in bxt_ddi_pll_disable()
3051 I915_WRITE(DDI_BUF_CTL(port), val); in intel_ddi_prepare_link_retrain()
3058 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_prepare_link_retrain()
3074 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_prepare_link_retrain()
3078 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); in intel_ddi_prepare_link_retrain()
3094 I915_WRITE(FDI_RX_CTL(PIPE_A), val); in intel_ddi_fdi_disable()
3099 I915_WRITE(FDI_RX_MISC(PIPE_A), val); in intel_ddi_fdi_disable()
3103 I915_WRITE(FDI_RX_CTL(PIPE_A), val); in intel_ddi_fdi_disable()
3107 I915_WRITE(FDI_RX_CTL(PIPE_A), val); in intel_ddi_fdi_disable()