1566 	uint32_t ctrl1, cfgcr1, cfgcr2;  in skl_ddi_pll_select()  local
1584 		cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |  in skl_ddi_pll_select()
1607 		cfgcr1 = cfgcr2 = 0;  in skl_ddi_pll_select()
1615 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;  in skl_ddi_pll_select()
2565 	u32 ctl, cfgcr1, cfgcr2;  member
2573 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2579 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2585 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2609 	I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);  in skl_ddi_pll_enable()
2611 	POSTING_READ(regs[pll->id].cfgcr1);  in skl_ddi_pll_enable()
2656 		hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);  in skl_ddi_pll_get_hw_state()