Lines Matching refs:INTEL_INFO
1138 if (INTEL_INFO(dev)->gen >= 4) { in intel_wait_for_pipe_off()
1261 if (INTEL_INFO(dev_priv->dev)->gen == 5) in assert_fdi_tx_pll_enabled()
1393 if (INTEL_INFO(dev)->gen >= 4) { in assert_planes_disabled()
1418 if (INTEL_INFO(dev)->gen >= 9) { in assert_sprites_disabled()
1432 } else if (INTEL_INFO(dev)->gen >= 7) { in assert_sprites_disabled()
1437 } else if (INTEL_INFO(dev)->gen >= 5) { in assert_sprites_disabled()
1698 BUG_ON(INTEL_INFO(dev)->gen >= 5); in i9xx_enable_pll()
1730 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_enable_pll()
1930 if (INTEL_INFO(dev)->gen < 5) in intel_disable_shared_dpll()
2212 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) in need_vtd_wa()
2319 if (INTEL_INFO(dev_priv)->gen >= 9) in intel_linear_alignment()
2324 else if (INTEL_INFO(dev_priv)->gen >= 4) in intel_linear_alignment()
2351 if (INTEL_INFO(dev)->gen >= 9) in intel_pin_and_fence_fb_obj()
2360 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, in intel_pin_and_fence_fb_obj()
2703 if (INTEL_INFO(dev)->gen >= 4) in i9xx_update_primary_plane()
2721 if (INTEL_INFO(dev)->gen < 4) { in i9xx_update_primary_plane()
2766 if (INTEL_INFO(dev)->gen >= 4 && in i9xx_update_primary_plane()
2775 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_primary_plane()
2805 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_primary_plane()
2933 if (INTEL_INFO(dev)->gen == 2) in intel_fb_stride_alignment()
3249 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in intel_prepare_reset()
3276 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { in intel_finish_reset()
3387 if (INTEL_INFO(dev)->gen >= 9) { in intel_update_pipe_config()
4294 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) in intel_get_shared_dpll()
5023 if (INTEL_INFO(dev)->gen >= 9) in haswell_crtc_enable()
5158 if (INTEL_INFO(dev)->gen >= 9) in haswell_crtc_disable()
5385 if (INTEL_INFO(dev_priv)->gen >= 9 || in intel_compute_max_dotclk()
5390 else if (INTEL_INFO(dev_priv)->gen < 4) in intel_compute_max_dotclk()
6522 if (INTEL_INFO(dev)->num_pipes == 2) in ironlake_check_fdi_lanes()
6655 if (INTEL_INFO(dev)->gen < 4) { in intel_crtc_compute_config()
6688 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && in intel_crtc_compute_config()
7254 if (INTEL_INFO(dev)->gen >= 5) { in intel_cpu_transcoder_set_m_n()
7263 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && in intel_cpu_transcoder_set_m_n()
7639 if (INTEL_INFO(dev)->gen >= 4) in i9xx_compute_dpll()
7653 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_compute_dpll()
7727 if (INTEL_INFO(dev)->gen > 3) in intel_set_pipe_timings()
7880 if (INTEL_INFO(dev)->gen < 4 || in i9xx_set_pipeconf()
7982 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) in i9xx_get_pfit_config()
7990 if (INTEL_INFO(dev)->gen < 4) { in i9xx_get_pfit_config()
8000 if (INTEL_INFO(dev)->gen < 5) in i9xx_get_pfit_config()
8057 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_initial_plane_config()
8069 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_initial_plane_config()
8168 if (INTEL_INFO(dev)->gen < 4) in i9xx_get_pipe_config()
8175 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_pipe_config()
8718 if (INTEL_INFO(dev)->gen > 6) { in intel_set_pipe_csc()
8764 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { in haswell_set_pipeconf()
9024 if (INTEL_INFO(dev)->gen >= 5) { in intel_cpu_transcoder_get_m_n()
9036 if (m2_n2 && INTEL_INFO(dev)->gen < 8 && in intel_cpu_transcoder_get_m_n()
9238 if (INTEL_INFO(dev)->gen >= 4) { in ironlake_get_initial_plane_config()
9859 if (INTEL_INFO(dev)->gen < 9 && in haswell_get_ddi_port_state()
9920 if (INTEL_INFO(dev)->gen >= 9) { in haswell_get_pipe_config()
9926 if (INTEL_INFO(dev)->gen >= 9) { in haswell_get_pipe_config()
9932 if (INTEL_INFO(dev)->gen >= 9) in haswell_get_pipe_config()
10755 if (INTEL_INFO(dev)->gen >= 6) in intel_mark_busy()
10769 if (INTEL_INFO(dev)->gen >= 6) in intel_mark_idle()
10895 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) in page_flip_finished()
11201 if (INTEL_INFO(ring->dev)->gen < 5) in use_mmio_flip()
11304 if (INTEL_INFO(mmio_flip->i915)->gen >= 9) in intel_do_mmio_flip()
11393 if (INTEL_INFO(dev)->gen >= 4) in __intel_pageflip_stall_check()
11465 if (INTEL_INFO(dev)->gen > 3 && in intel_crtc_page_flip()
11526 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in intel_crtc_page_flip()
11536 } else if (INTEL_INFO(dev)->gen >= 7) { in intel_crtc_page_flip()
11708 if (crtc_state && INTEL_INFO(dev)->gen >= 9 && in intel_plane_atomic_calc_changes()
11804 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && in intel_plane_atomic_calc_changes()
11911 if (INTEL_INFO(dev)->gen >= 9) { in intel_crtc_atomic_check()
11986 else if (INTEL_INFO(dev)->gen >= 5) in compute_baseline_pipe_bpp()
12559 if (INTEL_INFO(dev)->gen < 8) { in intel_pipe_config_compare()
12583 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || in intel_pipe_config_compare()
12606 if (INTEL_INFO(dev)->gen < 4) in intel_pipe_config_compare()
12642 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) in intel_pipe_config_compare()
12666 if (INTEL_INFO(dev)->gen < 9) in check_wm_state()
13490 INTEL_INFO(dev)->cursor_needs_physical) { in intel_prepare_plane_fb()
13525 !INTEL_INFO(dev)->cursor_needs_physical) { in intel_cleanup_plane_fb()
13573 if (INTEL_INFO(plane->dev)->gen >= 9) { in intel_check_primary_plane()
13646 else if (INTEL_INFO(dev)->gen >= 9) in intel_begin_crtc_commit()
13706 if (INTEL_INFO(dev)->gen >= 9) { in intel_primary_plane_create()
13716 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) in intel_primary_plane_create()
13719 if (INTEL_INFO(dev)->gen >= 9) { in intel_primary_plane_create()
13722 } else if (INTEL_INFO(dev)->gen >= 4) { in intel_primary_plane_create()
13735 if (INTEL_INFO(dev)->gen >= 4) in intel_primary_plane_create()
13749 if (INTEL_INFO(dev)->gen >= 9) in intel_create_rotation_property()
13844 else if (!INTEL_INFO(dev)->cursor_needs_physical) in intel_commit_cursor_plane()
13887 if (INTEL_INFO(dev)->gen >= 4) { in intel_cursor_plane_create()
13899 if (INTEL_INFO(dev)->gen >=9) in intel_cursor_plane_create()
13944 if (INTEL_INFO(dev)->gen >= 9) { in intel_crtc_init()
13979 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { in intel_crtc_init()
14079 if (INTEL_INFO(dev)->gen >= 9) in intel_crt_present()
14327 u32 gen = INTEL_INFO(dev)->gen; in intel_fb_pitch_limit()
14384 if (INTEL_INFO(dev)->gen < 9) { in intel_framebuffer_init()
14431 if (INTEL_INFO(dev)->gen > 3) { in intel_framebuffer_init()
14438 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { in intel_framebuffer_init()
14447 if (INTEL_INFO(dev)->gen < 4) { in intel_framebuffer_init()
14464 if (INTEL_INFO(dev)->gen < 5) { in intel_framebuffer_init()
14547 if (INTEL_INFO(dev)->gen >= 9) { in intel_init_display()
14683 switch (INTEL_INFO(dev)->gen) { in intel_init_display()
14932 if (INTEL_INFO(dev)->num_pipes == 0) in intel_modeset_init()
14981 INTEL_INFO(dev)->num_pipes, in intel_modeset_init()
14982 INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); in intel_modeset_init()
15065 if (INTEL_INFO(dev)->num_pipes == 1) in intel_check_plane_mapping()
15117 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { in intel_sanitize_crtc()
15640 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; in intel_modeset_vga_set_state()
15721 if (INTEL_INFO(dev)->num_pipes == 0) in intel_display_capture_error_state()
15744 if (INTEL_INFO(dev)->gen <= 3) { in intel_display_capture_error_state()
15748 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) in intel_display_capture_error_state()
15750 if (INTEL_INFO(dev)->gen >= 4) { in intel_display_capture_error_state()
15761 error->num_transcoders = INTEL_INFO(dev)->num_pipes; in intel_display_capture_error_state()
15801 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); in intel_display_print_error_state()
15815 if (INTEL_INFO(dev)->gen <= 3) { in intel_display_print_error_state()
15819 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) in intel_display_print_error_state()
15821 if (INTEL_INFO(dev)->gen >= 4) { in intel_display_print_error_state()