Lines Matching refs:intel_crtc
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
107 static void chv_prepare_pll(struct intel_crtc *crtc,
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) in intel_pipe_has_type()
951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in vlv_find_best_dpll()
1005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in chv_find_best_dpll()
1068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_active() local
1083 return intel_crtc->active && crtc->primary->state->fb && in intel_crtc_active()
1084 intel_crtc->config->base.adjusted_mode.crtc_clock; in intel_crtc_active()
1091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_pipe_to_cpu_transcoder() local
1093 return intel_crtc->config->cpu_transcoder; in intel_pipe_to_cpu_transcoder()
1131 static void intel_wait_for_pipe_off(struct intel_crtc *crtc) in intel_wait_for_pipe_off()
1190 intel_crtc_to_shared_dpll(struct intel_crtc *crtc) in intel_crtc_to_shared_dpll()
1598 static void vlv_enable_pll(struct intel_crtc *crtc, in vlv_enable_pll()
1637 static void chv_enable_pll(struct intel_crtc *crtc, in chv_enable_pll()
1678 struct intel_crtc *crtc; in intel_num_dvo_pipes()
1688 static void i9xx_enable_pll(struct intel_crtc *crtc) in i9xx_enable_pll()
1763 static void i9xx_disable_pll(struct intel_crtc *crtc) in i9xx_disable_pll()
1866 static void intel_prepare_shared_dpll(struct intel_crtc *crtc) in intel_prepare_shared_dpll()
1893 static void intel_enable_shared_dpll(struct intel_crtc *crtc) in intel_enable_shared_dpll()
1923 static void intel_disable_shared_dpll(struct intel_crtc *crtc) in intel_disable_shared_dpll()
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_enable_pch_transcoder() local
1973 intel_crtc_to_shared_dpll(intel_crtc)); in ironlake_enable_pch_transcoder()
1999 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) in ironlake_enable_pch_transcoder()
2008 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) in ironlake_enable_pch_transcoder()
2105 static void intel_enable_pipe(struct intel_crtc *crtc) in intel_enable_pipe()
2169 static void intel_disable_pipe(struct intel_crtc *crtc) in intel_disable_pipe()
2528 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, in intel_alloc_initial_plane_obj()
2601 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, in intel_find_initial_plane_obj() argument
2604 struct drm_device *dev = intel_crtc->base.dev; in intel_find_initial_plane_obj()
2607 struct intel_crtc *i; in intel_find_initial_plane_obj()
2609 struct drm_plane *primary = intel_crtc->base.primary; in intel_find_initial_plane_obj()
2611 struct drm_crtc_state *crtc_state = intel_crtc->base.state; in intel_find_initial_plane_obj()
2618 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { in intel_find_initial_plane_obj()
2632 if (c == &intel_crtc->base) in intel_find_initial_plane_obj()
2658 intel_pre_disable_primary(&intel_crtc->base); in intel_find_initial_plane_obj()
2659 intel_plane->disable_plane(primary, &intel_crtc->base); in intel_find_initial_plane_obj()
2680 primary->crtc = primary->state->crtc = &intel_crtc->base; in intel_find_initial_plane_obj()
2681 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); in intel_find_initial_plane_obj()
2691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_primary_plane() local
2695 int plane = intel_crtc->plane; in i9xx_update_primary_plane()
2722 if (intel_crtc->pipe == PIPE_B) in i9xx_update_primary_plane()
2729 ((intel_crtc->config->pipe_src_h - 1) << 16) | in i9xx_update_primary_plane()
2730 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2734 ((intel_crtc->config->pipe_src_h - 1) << 16) | in i9xx_update_primary_plane()
2735 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2776 intel_crtc->dspaddr_offset = in i9xx_update_primary_plane()
2781 linear_offset -= intel_crtc->dspaddr_offset; in i9xx_update_primary_plane()
2783 intel_crtc->dspaddr_offset = linear_offset; in i9xx_update_primary_plane()
2789 x += (intel_crtc->config->pipe_src_w - 1); in i9xx_update_primary_plane()
2790 y += (intel_crtc->config->pipe_src_h - 1); in i9xx_update_primary_plane()
2795 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + in i9xx_update_primary_plane()
2796 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in i9xx_update_primary_plane()
2799 intel_crtc->adjusted_x = x; in i9xx_update_primary_plane()
2800 intel_crtc->adjusted_y = y; in i9xx_update_primary_plane()
2807 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); in i9xx_update_primary_plane()
2821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_update_primary_plane() local
2825 int plane = intel_crtc->plane; in ironlake_update_primary_plane()
2881 intel_crtc->dspaddr_offset = in ironlake_update_primary_plane()
2886 linear_offset -= intel_crtc->dspaddr_offset; in ironlake_update_primary_plane()
2891 x += (intel_crtc->config->pipe_src_w - 1); in ironlake_update_primary_plane()
2892 y += (intel_crtc->config->pipe_src_h - 1); in ironlake_update_primary_plane()
2897 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + in ironlake_update_primary_plane()
2898 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in ironlake_update_primary_plane()
2902 intel_crtc->adjusted_x = x; in ironlake_update_primary_plane()
2903 intel_crtc->adjusted_y = y; in ironlake_update_primary_plane()
2909 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); in ironlake_update_primary_plane()
2981 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) in skl_detach_scaler() argument
2983 struct drm_device *dev = intel_crtc->base.dev; in skl_detach_scaler()
2986 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); in skl_detach_scaler()
2987 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); in skl_detach_scaler()
2988 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); in skl_detach_scaler()
2994 static void skl_detach_scalers(struct intel_crtc *intel_crtc) in skl_detach_scalers() argument
2999 scaler_state = &intel_crtc->config->scaler_state; in skl_detach_scalers()
3002 for (i = 0; i < intel_crtc->num_scalers; i++) { in skl_detach_scalers()
3004 skl_detach_scaler(intel_crtc, i); in skl_detach_scalers()
3095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in skylake_update_primary_plane() local
3099 int pipe = intel_crtc->pipe; in skylake_update_primary_plane()
3105 struct intel_crtc_state *crtc_state = intel_crtc->config; in skylake_update_primary_plane()
3166 intel_crtc->adjusted_x = x_offset; in skylake_update_primary_plane()
3167 intel_crtc->adjusted_y = y_offset; in skylake_update_primary_plane()
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_complete_page_flips() local
3216 enum plane plane = intel_crtc->plane; in intel_complete_page_flips()
3341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_has_pending_flip() local
3345 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) in intel_crtc_has_pending_flip()
3355 static void intel_update_pipe_config(struct intel_crtc *crtc, in intel_update_pipe_config()
3404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_fdi_normal_train() local
3405 int pipe = intel_crtc->pipe; in intel_fdi_normal_train()
3446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_link_train() local
3447 int pipe = intel_crtc->pipe; in ironlake_fdi_link_train()
3467 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in ironlake_fdi_link_train()
3546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in gen6_fdi_link_train() local
3547 int pipe = intel_crtc->pipe; in gen6_fdi_link_train()
3565 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in gen6_fdi_link_train()
3678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ivb_manual_fdi_link_train() local
3679 int pipe = intel_crtc->pipe; in ivb_manual_fdi_link_train()
3716 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in ivb_manual_fdi_link_train()
3792 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) in ironlake_fdi_pll_enable() argument
3794 struct drm_device *dev = intel_crtc->base.dev; in ironlake_fdi_pll_enable()
3796 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_enable()
3804 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in ironlake_fdi_pll_enable()
3829 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) in ironlake_fdi_pll_disable() argument
3831 struct drm_device *dev = intel_crtc->base.dev; in ironlake_fdi_pll_disable()
3833 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_disable()
3862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_disable() local
3863 int pipe = intel_crtc->pipe; in ironlake_fdi_disable()
3912 struct intel_crtc *crtc; in intel_has_pending_fb_unpin()
3934 static void page_flip_completed(struct intel_crtc *intel_crtc) in page_flip_completed() argument
3936 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); in page_flip_completed()
3937 struct intel_unpin_work *work = intel_crtc->unpin_work; in page_flip_completed()
3941 intel_crtc->unpin_work = NULL; in page_flip_completed()
3944 drm_send_vblank_event(intel_crtc->base.dev, in page_flip_completed()
3945 intel_crtc->pipe, in page_flip_completed()
3948 drm_crtc_vblank_put(&intel_crtc->base); in page_flip_completed()
3951 trace_i915_flip_complete(intel_crtc->plane, in page_flip_completed()
3966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_wait_for_pending_flips() local
3969 if (intel_crtc->unpin_work) { in intel_crtc_wait_for_pending_flips()
3971 page_flip_completed(intel_crtc); in intel_crtc_wait_for_pending_flips()
4072 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, in ironlake_pch_transcoder_set_timings()
4117 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) in ivybridge_update_fdi_bc_bifurcation() argument
4119 struct drm_device *dev = intel_crtc->base.dev; in ivybridge_update_fdi_bc_bifurcation()
4121 switch (intel_crtc->pipe) { in ivybridge_update_fdi_bc_bifurcation()
4125 if (intel_crtc->config->fdi_lanes > 2) in ivybridge_update_fdi_bc_bifurcation()
4152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_pch_enable() local
4153 int pipe = intel_crtc->pipe; in ironlake_pch_enable()
4159 ivybridge_update_fdi_bc_bifurcation(intel_crtc); in ironlake_pch_enable()
4177 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) in ironlake_pch_enable()
4191 intel_enable_shared_dpll(intel_crtc); in ironlake_pch_enable()
4195 ironlake_pch_transcoder_set_timings(intel_crtc, pipe); in ironlake_pch_enable()
4200 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { in ironlake_pch_enable()
4239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in lpt_pch_enable() local
4240 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in lpt_pch_enable()
4247 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); in lpt_pch_enable()
4252 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, in intel_get_shared_dpll()
4380 struct intel_crtc *intel_crtc = in skl_update_scaler() local
4405 intel_crtc->pipe, scaler_user, *scaler_id, in skl_update_scaler()
4420 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); in skl_update_scaler()
4428 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, in skl_update_scaler()
4445 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); in skl_update_scaler_crtc() local
4449 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); in skl_update_scaler_crtc()
4471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); in skl_update_scaler_plane() local
4480 intel_plane->base.base.id, intel_crtc->pipe, in skl_update_scaler_plane()
4525 static void skylake_scaler_disable(struct intel_crtc *crtc) in skylake_scaler_disable()
4533 static void skylake_pfit_enable(struct intel_crtc *crtc) in skylake_pfit_enable()
4561 static void ironlake_pfit_enable(struct intel_crtc *crtc) in ironlake_pfit_enable()
4582 void hsw_enable_ips(struct intel_crtc *crtc) in hsw_enable_ips()
4615 void hsw_disable_ips(struct intel_crtc *crtc) in hsw_disable_ips()
4645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_load_lut() local
4646 enum pipe pipe = intel_crtc->pipe; in intel_crtc_load_lut()
4655 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) in intel_crtc_load_lut()
4664 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && in intel_crtc_load_lut()
4667 hsw_disable_ips(intel_crtc); in intel_crtc_load_lut()
4680 (intel_crtc->lut_r[i] << 16) | in intel_crtc_load_lut()
4681 (intel_crtc->lut_g[i] << 8) | in intel_crtc_load_lut()
4682 intel_crtc->lut_b[i]); in intel_crtc_load_lut()
4686 hsw_enable_ips(intel_crtc); in intel_crtc_load_lut()
4689 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) in intel_crtc_dpms_overlay_disable() argument
4691 if (intel_crtc->overlay) { in intel_crtc_dpms_overlay_disable()
4692 struct drm_device *dev = intel_crtc->base.dev; in intel_crtc_dpms_overlay_disable()
4697 (void) intel_overlay_switch_off(intel_crtc->overlay); in intel_crtc_dpms_overlay_disable()
4722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_post_enable_primary() local
4723 int pipe = intel_crtc->pipe; in intel_post_enable_primary()
4739 hsw_enable_ips(intel_crtc); in intel_post_enable_primary()
4771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_pre_disable_primary() local
4772 int pipe = intel_crtc->pipe; in intel_pre_disable_primary()
4804 hsw_disable_ips(intel_crtc); in intel_pre_disable_primary()
4807 static void intel_post_plane_update(struct intel_crtc *crtc) in intel_post_plane_update()
4838 static void intel_pre_plane_update(struct intel_crtc *crtc) in intel_pre_plane_update()
4876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_disable_planes() local
4878 int pipe = intel_crtc->pipe; in intel_crtc_disable_planes()
4880 intel_crtc_dpms_overlay_disable(intel_crtc); in intel_crtc_disable_planes()
4897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_enable() local
4899 int pipe = intel_crtc->pipe; in ironlake_crtc_enable()
4901 if (WARN_ON(intel_crtc->active)) in ironlake_crtc_enable()
4904 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_enable()
4905 intel_prepare_shared_dpll(intel_crtc); in ironlake_crtc_enable()
4907 if (intel_crtc->config->has_dp_encoder) in ironlake_crtc_enable()
4908 intel_dp_set_m_n(intel_crtc, M1_N1); in ironlake_crtc_enable()
4910 intel_set_pipe_timings(intel_crtc); in ironlake_crtc_enable()
4912 if (intel_crtc->config->has_pch_encoder) { in ironlake_crtc_enable()
4913 intel_cpu_transcoder_set_m_n(intel_crtc, in ironlake_crtc_enable()
4914 &intel_crtc->config->fdi_m_n, NULL); in ironlake_crtc_enable()
4919 intel_crtc->active = true; in ironlake_crtc_enable()
4928 if (intel_crtc->config->has_pch_encoder) { in ironlake_crtc_enable()
4932 ironlake_fdi_pll_enable(intel_crtc); in ironlake_crtc_enable()
4938 ironlake_pfit_enable(intel_crtc); in ironlake_crtc_enable()
4947 intel_enable_pipe(intel_crtc); in ironlake_crtc_enable()
4949 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_enable()
4959 cpt_verify_modeset(dev, intel_crtc->pipe); in ironlake_crtc_enable()
4963 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) in hsw_crtc_supports_ips()
4972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_enable() local
4974 int pipe = intel_crtc->pipe, hsw_workaround_pipe; in haswell_crtc_enable()
4977 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); in haswell_crtc_enable()
4979 if (WARN_ON(intel_crtc->active)) in haswell_crtc_enable()
4982 if (intel_crtc_to_shared_dpll(intel_crtc)) in haswell_crtc_enable()
4983 intel_enable_shared_dpll(intel_crtc); in haswell_crtc_enable()
4985 if (intel_crtc->config->has_dp_encoder) in haswell_crtc_enable()
4986 intel_dp_set_m_n(intel_crtc, M1_N1); in haswell_crtc_enable()
4988 intel_set_pipe_timings(intel_crtc); in haswell_crtc_enable()
4990 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { in haswell_crtc_enable()
4991 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), in haswell_crtc_enable()
4992 intel_crtc->config->pixel_multiplier - 1); in haswell_crtc_enable()
4995 if (intel_crtc->config->has_pch_encoder) { in haswell_crtc_enable()
4996 intel_cpu_transcoder_set_m_n(intel_crtc, in haswell_crtc_enable()
4997 &intel_crtc->config->fdi_m_n, NULL); in haswell_crtc_enable()
5004 intel_crtc->active = true; in haswell_crtc_enable()
5014 if (intel_crtc->config->has_pch_encoder) { in haswell_crtc_enable()
5021 intel_ddi_enable_pipe_clock(intel_crtc); in haswell_crtc_enable()
5024 skylake_pfit_enable(intel_crtc); in haswell_crtc_enable()
5026 ironlake_pfit_enable(intel_crtc); in haswell_crtc_enable()
5039 intel_enable_pipe(intel_crtc); in haswell_crtc_enable()
5041 if (intel_crtc->config->has_pch_encoder) in haswell_crtc_enable()
5044 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi) in haswell_crtc_enable()
5064 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) in ironlake_pfit_disable()
5083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_disable() local
5085 int pipe = intel_crtc->pipe; in ironlake_crtc_disable()
5094 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_disable()
5097 intel_disable_pipe(intel_crtc); in ironlake_crtc_disable()
5099 ironlake_pfit_disable(intel_crtc, false); in ironlake_crtc_disable()
5101 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_disable()
5108 if (intel_crtc->config->has_pch_encoder) { in ironlake_crtc_disable()
5126 ironlake_fdi_pll_disable(intel_crtc); in ironlake_crtc_disable()
5134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_disable() local
5136 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in haswell_crtc_disable()
5137 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); in haswell_crtc_disable()
5147 if (intel_crtc->config->has_pch_encoder) in haswell_crtc_disable()
5150 intel_disable_pipe(intel_crtc); in haswell_crtc_disable()
5152 if (intel_crtc->config->dp_encoder_is_mst) in haswell_crtc_disable()
5159 skylake_scaler_disable(intel_crtc); in haswell_crtc_disable()
5161 ironlake_pfit_disable(intel_crtc, false); in haswell_crtc_disable()
5164 intel_ddi_disable_pipe_clock(intel_crtc); in haswell_crtc_disable()
5166 if (intel_crtc->config->has_pch_encoder) { in haswell_crtc_disable()
5176 static void i9xx_pfit_enable(struct intel_crtc *crtc) in i9xx_pfit_enable()
5304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in get_crtc_power_domains() local
5305 enum pipe pipe = intel_crtc->pipe; in get_crtc_power_domains()
5316 if (intel_crtc->config->pch_pfit.enabled || in get_crtc_power_domains()
5317 intel_crtc->config->pch_pfit.force_thru) in get_crtc_power_domains()
5329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in modeset_get_crtc_power_domains() local
5333 old_domains = intel_crtc->enabled_power_domains; in modeset_get_crtc_power_domains()
5334 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); in modeset_get_crtc_power_domains()
6025 struct intel_crtc *intel_crtc; in intel_mode_max_pixclk() local
6029 for_each_intel_crtc(dev, intel_crtc) { in intel_mode_max_pixclk()
6030 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in intel_mode_max_pixclk()
6141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in valleyview_crtc_enable() local
6143 int pipe = intel_crtc->pipe; in valleyview_crtc_enable()
6146 if (WARN_ON(intel_crtc->active)) in valleyview_crtc_enable()
6149 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); in valleyview_crtc_enable()
6151 if (intel_crtc->config->has_dp_encoder) in valleyview_crtc_enable()
6152 intel_dp_set_m_n(intel_crtc, M1_N1); in valleyview_crtc_enable()
6154 intel_set_pipe_timings(intel_crtc); in valleyview_crtc_enable()
6163 i9xx_set_pipeconf(intel_crtc); in valleyview_crtc_enable()
6165 intel_crtc->active = true; in valleyview_crtc_enable()
6175 chv_prepare_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
6176 chv_enable_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
6178 vlv_prepare_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
6179 vlv_enable_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
6187 i9xx_pfit_enable(intel_crtc); in valleyview_crtc_enable()
6191 intel_enable_pipe(intel_crtc); in valleyview_crtc_enable()
6200 static void i9xx_set_pll_dividers(struct intel_crtc *crtc) in i9xx_set_pll_dividers()
6213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_enable() local
6215 int pipe = intel_crtc->pipe; in i9xx_crtc_enable()
6217 if (WARN_ON(intel_crtc->active)) in i9xx_crtc_enable()
6220 i9xx_set_pll_dividers(intel_crtc); in i9xx_crtc_enable()
6222 if (intel_crtc->config->has_dp_encoder) in i9xx_crtc_enable()
6223 intel_dp_set_m_n(intel_crtc, M1_N1); in i9xx_crtc_enable()
6225 intel_set_pipe_timings(intel_crtc); in i9xx_crtc_enable()
6227 i9xx_set_pipeconf(intel_crtc); in i9xx_crtc_enable()
6229 intel_crtc->active = true; in i9xx_crtc_enable()
6238 i9xx_enable_pll(intel_crtc); in i9xx_crtc_enable()
6240 i9xx_pfit_enable(intel_crtc); in i9xx_crtc_enable()
6245 intel_enable_pipe(intel_crtc); in i9xx_crtc_enable()
6254 static void i9xx_pfit_disable(struct intel_crtc *crtc) in i9xx_pfit_disable()
6273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_disable() local
6275 int pipe = intel_crtc->pipe; in i9xx_crtc_disable()
6291 intel_disable_pipe(intel_crtc); in i9xx_crtc_disable()
6293 i9xx_pfit_disable(intel_crtc); in i9xx_crtc_disable()
6299 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { in i9xx_crtc_disable()
6305 i9xx_disable_pll(intel_crtc); in i9xx_crtc_disable()
6318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_disable_noatomic() local
6323 if (!intel_crtc->active) in intel_crtc_disable_noatomic()
6335 intel_crtc->active = false; in intel_crtc_disable_noatomic()
6337 intel_disable_shared_dpll(intel_crtc); in intel_crtc_disable_noatomic()
6339 domains = intel_crtc->enabled_power_domains; in intel_crtc_disable_noatomic()
6342 intel_crtc->enabled_power_domains = 0; in intel_crtc_disable_noatomic()
6501 struct intel_crtc *other_crtc; in ironlake_check_fdi_lanes()
6569 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, in ironlake_fdi_compute_config() argument
6572 struct drm_device *dev = intel_crtc->base.dev; in ironlake_fdi_compute_config()
6597 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, in ironlake_fdi_compute_config()
6598 intel_crtc->pipe, pipe_config); in ironlake_fdi_compute_config()
6636 static void hsw_compute_ips_config(struct intel_crtc *crtc, in hsw_compute_ips_config()
6647 static int intel_crtc_compute_config(struct intel_crtc *crtc, in intel_crtc_compute_config()
7174 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, in i9xx_update_pll_dividers()
7232 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_set_m_n()
7245 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_set_m_n()
7279 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) in intel_dp_set_m_n()
7304 static void vlv_compute_dpll(struct intel_crtc *crtc, in vlv_compute_dpll()
7327 static void vlv_prepare_pll(struct intel_crtc *crtc, in vlv_prepare_pll()
7418 static void chv_compute_dpll(struct intel_crtc *crtc, in chv_compute_dpll()
7431 static void chv_prepare_pll(struct intel_crtc *crtc, in chv_prepare_pll()
7548 struct intel_crtc *crtc = in vlv_force_pll_on()
7583 static void i9xx_compute_dpll(struct intel_crtc *crtc, in i9xx_compute_dpll()
7660 static void i8xx_compute_dpll(struct intel_crtc *crtc, in i8xx_compute_dpll()
7698 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) in intel_set_pipe_timings() argument
7700 struct drm_device *dev = intel_crtc->base.dev; in intel_set_pipe_timings()
7702 enum pipe pipe = intel_crtc->pipe; in intel_set_pipe_timings()
7703 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in intel_set_pipe_timings()
7704 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; in intel_set_pipe_timings()
7718 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) in intel_set_pipe_timings()
7762 ((intel_crtc->config->pipe_src_w - 1) << 16) | in intel_set_pipe_timings()
7763 (intel_crtc->config->pipe_src_h - 1)); in intel_set_pipe_timings()
7766 static void intel_get_pipe_timings(struct intel_crtc *crtc, in intel_get_pipe_timings()
7832 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) in i9xx_set_pipeconf() argument
7834 struct drm_device *dev = intel_crtc->base.dev; in i9xx_set_pipeconf()
7840 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_set_pipeconf()
7841 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_set_pipeconf()
7842 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
7844 if (intel_crtc->config->double_wide) in i9xx_set_pipeconf()
7850 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) in i9xx_set_pipeconf()
7854 switch (intel_crtc->config->pipe_bpp) { in i9xx_set_pipeconf()
7871 if (intel_crtc->lowfreq_avail) { in i9xx_set_pipeconf()
7879 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in i9xx_set_pipeconf()
7881 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) in i9xx_set_pipeconf()
7888 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) in i9xx_set_pipeconf()
7891 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); in i9xx_set_pipeconf()
7892 POSTING_READ(PIPECONF(intel_crtc->pipe)); in i9xx_set_pipeconf()
7895 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, in i9xx_crtc_compute_clock()
7975 static void i9xx_get_pfit_config(struct intel_crtc *crtc, in i9xx_get_pfit_config()
8005 static void vlv_crtc_clock_get(struct intel_crtc *crtc, in vlv_crtc_clock_get()
8033 i9xx_get_initial_plane_config(struct intel_crtc *crtc, in i9xx_get_initial_plane_config()
8101 static void chv_crtc_clock_get(struct intel_crtc *crtc, in chv_crtc_clock_get()
8131 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, in i9xx_get_pipe_config()
8636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_set_pipeconf() local
8637 int pipe = intel_crtc->pipe; in ironlake_set_pipeconf()
8642 switch (intel_crtc->config->pipe_bpp) { in ironlake_set_pipeconf()
8660 if (intel_crtc->config->dither) in ironlake_set_pipeconf()
8663 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in ironlake_set_pipeconf()
8668 if (intel_crtc->config->limited_color_range) in ironlake_set_pipeconf()
8686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_set_pipe_csc() local
8687 int pipe = intel_crtc->pipe; in intel_set_pipe_csc()
8697 if (intel_crtc->config->limited_color_range) in intel_set_pipe_csc()
8721 if (intel_crtc->config->limited_color_range) in intel_set_pipe_csc()
8732 if (intel_crtc->config->limited_color_range) in intel_set_pipe_csc()
8743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_set_pipeconf() local
8744 enum pipe pipe = intel_crtc->pipe; in haswell_set_pipeconf()
8745 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in haswell_set_pipeconf()
8750 if (IS_HASWELL(dev) && intel_crtc->config->dither) in haswell_set_pipeconf()
8753 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in haswell_set_pipeconf()
8761 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); in haswell_set_pipeconf()
8762 POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); in haswell_set_pipeconf()
8767 switch (intel_crtc->config->pipe_bpp) { in haswell_set_pipeconf()
8785 if (intel_crtc->config->dither) in haswell_set_pipeconf()
8837 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, in ironlake_compute_dpll() argument
8842 struct drm_crtc *crtc = &intel_crtc->base; in ironlake_compute_dpll()
8933 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, in ironlake_crtc_compute_clock()
8999 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_get_m_n()
9015 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_get_m_n()
9057 void intel_dp_get_m_n(struct intel_crtc *crtc, in intel_dp_get_m_n()
9068 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, in ironlake_get_fdi_m_n_config()
9075 static void skylake_get_pfit_config(struct intel_crtc *crtc, in skylake_get_pfit_config()
9106 skylake_get_initial_plane_config(struct intel_crtc *crtc, in skylake_get_initial_plane_config()
9189 static void ironlake_get_pfit_config(struct intel_crtc *crtc, in ironlake_get_pfit_config()
9214 ironlake_get_initial_plane_config(struct intel_crtc *crtc, in ironlake_get_initial_plane_config()
9282 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, in ironlake_get_pipe_config()
9367 struct intel_crtc *crtc; in assert_can_disable_lcpll()
9598 struct intel_crtc *intel_crtc; in ilk_max_pixel_rate() local
9602 for_each_intel_crtc(state->dev, intel_crtc) { in ilk_max_pixel_rate()
9605 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in ilk_max_pixel_rate()
9745 static int haswell_crtc_compute_clock(struct intel_crtc *crtc, in haswell_crtc_compute_clock()
9827 static void haswell_get_ddi_port_state(struct intel_crtc *crtc, in haswell_get_ddi_port_state()
9871 static bool haswell_get_pipe_config(struct intel_crtc *crtc, in haswell_get_pipe_config()
9956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i845_update_cursor() local
9960 unsigned int width = intel_crtc->base.cursor->state->crtc_w; in i845_update_cursor()
9961 unsigned int height = intel_crtc->base.cursor->state->crtc_h; in i845_update_cursor()
9985 if (intel_crtc->cursor_cntl != 0 && in i845_update_cursor()
9986 (intel_crtc->cursor_base != base || in i845_update_cursor()
9987 intel_crtc->cursor_size != size || in i845_update_cursor()
9988 intel_crtc->cursor_cntl != cntl)) { in i845_update_cursor()
9994 intel_crtc->cursor_cntl = 0; in i845_update_cursor()
9997 if (intel_crtc->cursor_base != base) { in i845_update_cursor()
9999 intel_crtc->cursor_base = base; in i845_update_cursor()
10002 if (intel_crtc->cursor_size != size) { in i845_update_cursor()
10004 intel_crtc->cursor_size = size; in i845_update_cursor()
10007 if (intel_crtc->cursor_cntl != cntl) { in i845_update_cursor()
10010 intel_crtc->cursor_cntl = cntl; in i845_update_cursor()
10018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_cursor() local
10019 int pipe = intel_crtc->pipe; in i9xx_update_cursor()
10024 switch (intel_crtc->base.cursor->state->crtc_w) { in i9xx_update_cursor()
10035 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); in i9xx_update_cursor()
10047 if (intel_crtc->cursor_cntl != cntl) { in i9xx_update_cursor()
10050 intel_crtc->cursor_cntl = cntl; in i9xx_update_cursor()
10057 intel_crtc->cursor_base = base; in i9xx_update_cursor()
10066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_update_cursor() local
10067 int pipe = intel_crtc->pipe; in intel_crtc_update_cursor()
10073 base = intel_crtc->cursor_addr; in intel_crtc_update_cursor()
10075 if (x >= intel_crtc->config->pipe_src_w) in intel_crtc_update_cursor()
10078 if (y >= intel_crtc->config->pipe_src_h) in intel_crtc_update_cursor()
10155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_gamma_set() local
10158 intel_crtc->lut_r[i] = red[i] >> 8; in intel_crtc_gamma_set()
10159 intel_crtc->lut_g[i] = green[i] >> 8; in intel_crtc_gamma_set()
10160 intel_crtc->lut_b[i] = blue[i] >> 8; in intel_crtc_gamma_set()
10323 struct intel_crtc *intel_crtc; in intel_get_load_detect_pipe() local
10404 intel_crtc = to_intel_crtc(crtc); in intel_get_load_detect_pipe()
10424 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in intel_get_load_detect_pipe()
10469 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_get_load_detect_pipe()
10493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_release_load_detect_pipe() local
10514 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); in intel_release_load_detect_pipe()
10567 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, in i9xx_crtc_clock_get()
10675 static void ironlake_pch_clock_get(struct intel_crtc *crtc, in ironlake_pch_clock_get()
10699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_mode_get() local
10700 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in intel_crtc_mode_get()
10707 enum pipe pipe = intel_crtc->pipe; in intel_crtc_mode_get()
10725 i9xx_crtc_clock_get(intel_crtc, &pipe_config); in intel_crtc_mode_get()
10782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_destroy() local
10787 work = intel_crtc->unpin_work; in intel_crtc_destroy()
10788 intel_crtc->unpin_work = NULL; in intel_crtc_destroy()
10798 kfree(intel_crtc); in intel_crtc_destroy()
10805 struct intel_crtc *crtc = to_intel_crtc(work->crtc); in intel_unpin_work_fn()
10829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in do_intel_finish_page_flip() local
10834 if (intel_crtc == NULL) in do_intel_finish_page_flip()
10842 work = intel_crtc->unpin_work; in do_intel_finish_page_flip()
10852 page_flip_completed(intel_crtc); in do_intel_finish_page_flip()
10879 static bool page_flip_finished(struct intel_crtc *crtc) in page_flip_finished()
10922 struct intel_crtc *intel_crtc = in intel_prepare_page_flip() local
10936 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) in intel_prepare_page_flip()
10937 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); in intel_prepare_page_flip()
10958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen2_queue_flip() local
10969 if (intel_crtc->plane) in intel_gen2_queue_flip()
10976 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen2_queue_flip()
10978 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen2_queue_flip()
10981 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen2_queue_flip()
10993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen3_queue_flip() local
11001 if (intel_crtc->plane) in intel_gen3_queue_flip()
11008 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen3_queue_flip()
11010 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen3_queue_flip()
11013 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen3_queue_flip()
11026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen4_queue_flip() local
11039 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen4_queue_flip()
11041 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | in intel_gen4_queue_flip()
11049 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen4_queue_flip()
11052 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen4_queue_flip()
11065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen6_queue_flip() local
11074 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen6_queue_flip()
11076 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen6_queue_flip()
11085 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen6_queue_flip()
11088 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen6_queue_flip()
11100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen7_queue_flip() local
11104 switch (intel_crtc->plane) { in intel_gen7_queue_flip()
11180 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen7_queue_flip()
11183 intel_mark_page_flip_active(intel_crtc->unpin_work); in intel_gen7_queue_flip()
11214 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, in skl_do_mmio_flip() argument
11217 struct drm_device *dev = intel_crtc->base.dev; in skl_do_mmio_flip()
11219 struct drm_framebuffer *fb = intel_crtc->base.primary->fb; in skl_do_mmio_flip()
11220 const enum pipe pipe = intel_crtc->pipe; in skl_do_mmio_flip()
11260 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, in ilk_do_mmio_flip() argument
11263 struct drm_device *dev = intel_crtc->base.dev; in ilk_do_mmio_flip()
11266 to_intel_framebuffer(intel_crtc->base.primary->fb); in ilk_do_mmio_flip()
11271 reg = DSPCNTR(intel_crtc->plane); in ilk_do_mmio_flip()
11281 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); in ilk_do_mmio_flip()
11282 POSTING_READ(DSPSURF(intel_crtc->plane)); in ilk_do_mmio_flip()
11291 struct intel_crtc *crtc = mmio_flip->crtc; in intel_do_mmio_flip()
11367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __intel_pageflip_stall_check() local
11368 struct intel_unpin_work *work = intel_crtc->unpin_work; in __intel_pageflip_stall_check()
11394 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); in __intel_pageflip_stall_check()
11396 addr = I915_READ(DSPADDR(intel_crtc->plane)); in __intel_pageflip_stall_check()
11409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_check_page_flip() local
11418 work = intel_crtc->unpin_work; in intel_check_page_flip()
11422 page_flip_completed(intel_crtc); in intel_check_page_flip()
11440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_page_flip() local
11442 enum pipe pipe = intel_crtc->pipe; in intel_crtc_page_flip()
11488 if (intel_crtc->unpin_work) { in intel_crtc_page_flip()
11494 page_flip_completed(intel_crtc); in intel_crtc_page_flip()
11504 intel_crtc->unpin_work = work; in intel_crtc_page_flip()
11507 if (atomic_read(&intel_crtc->unpin_work_count) >= 2) in intel_crtc_page_flip()
11523 atomic_inc(&intel_crtc->unpin_work_count); in intel_crtc_page_flip()
11524 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); in intel_crtc_page_flip()
11559 work->gtt_offset += intel_crtc->dspaddr_offset; in intel_crtc_page_flip()
11594 intel_fbc_disable_crtc(intel_crtc); in intel_crtc_page_flip()
11598 trace_i915_flip_request(intel_crtc->plane, obj); in intel_crtc_page_flip()
11607 atomic_dec(&intel_crtc->unpin_work_count); in intel_crtc_page_flip()
11617 intel_crtc->unpin_work = NULL; in intel_crtc_page_flip()
11693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_plane_atomic_calc_changes() local
11699 int idx = intel_crtc->base.base.id, ret; in intel_plane_atomic_calc_changes()
11723 intel_crtc->atomic.disabled_planes |= 1 << i; in intel_plane_atomic_calc_changes()
11748 intel_crtc->atomic.update_wm_pre = true; in intel_plane_atomic_calc_changes()
11751 intel_crtc->atomic.disable_cxsr = true; in intel_plane_atomic_calc_changes()
11753 intel_crtc->atomic.wait_vblank = true; in intel_plane_atomic_calc_changes()
11754 intel_crtc->atomic.update_wm_post = true; in intel_plane_atomic_calc_changes()
11757 intel_crtc->atomic.update_wm_post = true; in intel_plane_atomic_calc_changes()
11761 intel_crtc->atomic.wait_vblank = true; in intel_plane_atomic_calc_changes()
11762 intel_crtc->atomic.disable_cxsr = true; in intel_plane_atomic_calc_changes()
11765 intel_crtc->atomic.update_wm_pre = true; in intel_plane_atomic_calc_changes()
11769 intel_crtc->atomic.fb_bits |= in intel_plane_atomic_calc_changes()
11774 intel_crtc->atomic.wait_for_flips = true; in intel_plane_atomic_calc_changes()
11775 intel_crtc->atomic.pre_disable_primary = turn_off; in intel_plane_atomic_calc_changes()
11776 intel_crtc->atomic.post_enable_primary = turn_on; in intel_plane_atomic_calc_changes()
11787 intel_crtc->atomic.disable_ips = true; in intel_plane_atomic_calc_changes()
11789 intel_crtc->atomic.disable_fbc = true; in intel_plane_atomic_calc_changes()
11805 dev_priv->fbc.crtc == intel_crtc && in intel_plane_atomic_calc_changes()
11807 intel_crtc->atomic.disable_fbc = true; in intel_plane_atomic_calc_changes()
11815 intel_crtc->atomic.wait_vblank = true; in intel_plane_atomic_calc_changes()
11817 intel_crtc->atomic.update_fbc |= visible || mode_changed; in intel_plane_atomic_calc_changes()
11823 intel_crtc->atomic.wait_vblank = true; in intel_plane_atomic_calc_changes()
11824 intel_crtc->atomic.update_sprite_watermarks |= in intel_plane_atomic_calc_changes()
11840 struct intel_crtc *crtc, in check_single_encoder_cloning()
11862 struct intel_crtc *crtc) in check_encoder_cloning()
11886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_atomic_check() local
11893 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { in intel_crtc_atomic_check()
11899 intel_crtc->atomic.update_wm_post = true; in intel_crtc_atomic_check()
11904 ret = dev_priv->display.crtc_compute_clock(intel_crtc, in intel_crtc_atomic_check()
11916 ret = intel_atomic_setup_scalers(dev, intel_crtc, in intel_crtc_atomic_check()
11975 compute_baseline_pipe_bpp(struct intel_crtc *crtc, in compute_baseline_pipe_bpp()
12019 static void intel_dump_pipe_config(struct intel_crtc *crtc, in intel_dump_pipe_config()
12379 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ argument
12380 list_for_each_entry((intel_crtc), \
12383 if (mask & (1 <<(intel_crtc)->pipe))
12663 struct intel_crtc *intel_crtc; in check_wm_state() local
12672 for_each_intel_crtc(dev, intel_crtc) { in check_wm_state()
12674 const enum pipe pipe = intel_crtc->pipe; in check_wm_state()
12676 if (!intel_crtc->active) in check_wm_state()
12780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in check_crtc_state() local
12797 active = dev_priv->display.get_pipe_config(intel_crtc, in check_crtc_state()
12801 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in check_crtc_state()
12802 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in check_crtc_state()
12809 I915_STATE_WARN(intel_crtc->active != crtc->state->active, in check_crtc_state()
12811 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); in check_crtc_state()
12821 I915_STATE_WARN(active && intel_crtc->pipe != pipe, in check_crtc_state()
12836 intel_dump_pipe_config(intel_crtc, pipe_config, in check_crtc_state()
12838 intel_dump_pipe_config(intel_crtc, sw_config, in check_crtc_state()
12848 struct intel_crtc *crtc; in check_shared_dpll_state()
12916 static void update_scanline_offset(struct intel_crtc *crtc) in update_scanline_offset()
12959 struct intel_crtc *intel_crtc; in intel_modeset_clear_plls() local
12971 intel_crtc = to_intel_crtc(crtc); in intel_modeset_clear_plls()
12983 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); in intel_modeset_clear_plls()
12996 struct intel_crtc *intel_crtc; in haswell_mode_set_planes_workaround() local
13005 intel_crtc = to_intel_crtc(crtc); in haswell_mode_set_planes_workaround()
13015 first_pipe = intel_crtc->pipe; in haswell_mode_set_planes_workaround()
13024 for_each_intel_crtc(state->dev, intel_crtc) { in haswell_mode_set_planes_workaround()
13027 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); in haswell_mode_set_planes_workaround()
13041 enabled_pipe = intel_crtc->pipe; in haswell_mode_set_planes_workaround()
13241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_atomic_commit() local
13247 intel_pre_plane_update(intel_crtc); in intel_atomic_commit()
13252 intel_crtc->active = false; in intel_atomic_commit()
13253 intel_disable_shared_dpll(intel_crtc); in intel_atomic_commit()
13270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_atomic_commit() local
13289 intel_pre_plane_update(intel_crtc); in intel_atomic_commit()
13296 intel_post_plane_update(intel_crtc); in intel_atomic_commit()
13411 struct intel_crtc *crtc; in ibx_pch_dpll_disable()
13533 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) in skl_max_scale() argument
13540 if (!intel_crtc || !crtc_state) in skl_max_scale()
13543 dev = intel_crtc->base.dev; in skl_max_scale()
13597 struct intel_crtc *intel_crtc; in intel_commit_primary_plane() local
13601 intel_crtc = to_intel_crtc(crtc); in intel_commit_primary_plane()
13629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_begin_crtc_commit() local
13634 if (intel_crtc->atomic.update_wm_pre) in intel_begin_crtc_commit()
13639 intel_pipe_update_start(intel_crtc); in intel_begin_crtc_commit()
13645 intel_update_pipe_config(intel_crtc, old_intel_state); in intel_begin_crtc_commit()
13647 skl_detach_scalers(intel_crtc); in intel_begin_crtc_commit()
13653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_finish_crtc_commit() local
13656 intel_pipe_update_end(intel_crtc); in intel_finish_crtc_commit()
13835 struct intel_crtc *intel_crtc; in intel_commit_cursor_plane() local
13840 intel_crtc = to_intel_crtc(crtc); in intel_commit_cursor_plane()
13849 intel_crtc->cursor_addr = addr; in intel_commit_cursor_plane()
13907 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, in skl_init_scalers() argument
13914 for (i = 0; i < intel_crtc->num_scalers; i++) { in skl_init_scalers()
13926 struct intel_crtc *intel_crtc; in intel_crtc_init() local
13932 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); in intel_crtc_init()
13933 if (intel_crtc == NULL) in intel_crtc_init()
13939 intel_crtc->config = crtc_state; in intel_crtc_init()
13940 intel_crtc->base.state = &crtc_state->base; in intel_crtc_init()
13941 crtc_state->base.crtc = &intel_crtc->base; in intel_crtc_init()
13946 intel_crtc->num_scalers = 1; in intel_crtc_init()
13948 intel_crtc->num_scalers = SKL_NUM_SCALERS; in intel_crtc_init()
13950 skl_init_scalers(dev, intel_crtc, crtc_state); in intel_crtc_init()
13961 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, in intel_crtc_init()
13966 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); in intel_crtc_init()
13968 intel_crtc->lut_r[i] = i; in intel_crtc_init()
13969 intel_crtc->lut_g[i] = i; in intel_crtc_init()
13970 intel_crtc->lut_b[i] = i; in intel_crtc_init()
13977 intel_crtc->pipe = pipe; in intel_crtc_init()
13978 intel_crtc->plane = pipe; in intel_crtc_init()
13981 intel_crtc->plane = !pipe; in intel_crtc_init()
13984 intel_crtc->cursor_base = ~0; in intel_crtc_init()
13985 intel_crtc->cursor_cntl = ~0; in intel_crtc_init()
13986 intel_crtc->cursor_size = ~0; in intel_crtc_init()
13988 intel_crtc->wm.cxsr_allowed = true; in intel_crtc_init()
13991 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); in intel_crtc_init()
13992 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; in intel_crtc_init()
13993 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; in intel_crtc_init()
13995 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); in intel_crtc_init()
13997 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); in intel_crtc_init()
14006 kfree(intel_crtc); in intel_crtc_init()
14027 struct intel_crtc *crtc; in intel_get_pipe_from_crtc_id()
14914 struct intel_crtc *crtc; in intel_modeset_init()
15059 intel_check_plane_mapping(struct intel_crtc *crtc) in intel_check_plane_mapping()
15077 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) in intel_crtc_has_encoders()
15088 static void intel_sanitize_crtc(struct intel_crtc *crtc) in intel_sanitize_crtc()
15282 static void readout_plane_state(struct intel_crtc *crtc) in readout_plane_state()
15299 struct intel_crtc *crtc; in intel_modeset_readout_hw_state()
15417 struct intel_crtc *crtc; in intel_modeset_setup_hw_state()
15849 struct intel_crtc *crtc; in intel_modeset_preclose()