1387 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);  in intel_dp_compute_config()  local
1427 			intel_gmch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1430 			intel_pch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1545 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);  in ironlake_set_pll_cpu_edp()
1586 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);  in intel_dp_prepare()
2279 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);  in intel_dp_get_config()
2363 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);  in intel_disable_dp()
2405 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);  in chv_data_lane_soft_reset()
2573 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);  in intel_enable_dp()
2712 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);  in vlv_init_panel_power_sequencer()
2753 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);  in vlv_pre_enable_dp()  local
2755 	int pipe = intel_crtc->pipe;  in vlv_pre_enable_dp()
2781 	struct intel_crtc *intel_crtc =  in vlv_dp_pre_pll_enable()  local
2784 	int pipe = intel_crtc->pipe;  in vlv_dp_pre_pll_enable()
2812 	struct intel_crtc *intel_crtc =  in chv_pre_enable_dp()  local
2815 	int pipe = intel_crtc->pipe;  in chv_pre_enable_dp()
2826 	if (intel_crtc->config->lane_count > 2) {  in chv_pre_enable_dp()
2833 	for (i = 0; i < intel_crtc->config->lane_count; i++) {  in chv_pre_enable_dp()
2835 		if (intel_crtc->config->lane_count == 1)  in chv_pre_enable_dp()
2844 	if (intel_crtc->config->port_clock > 270000)  in chv_pre_enable_dp()
2846 	else if (intel_crtc->config->port_clock > 135000)  in chv_pre_enable_dp()
2848 	else if (intel_crtc->config->port_clock > 67500)  in chv_pre_enable_dp()
2850 	else if (intel_crtc->config->port_clock > 33750)  in chv_pre_enable_dp()
2859 	if (intel_crtc->config->lane_count > 2) {  in chv_pre_enable_dp()
2872 	if (intel_crtc->config->lane_count > 2) {  in chv_pre_enable_dp()
2900 	struct intel_crtc *intel_crtc =  in chv_dp_pre_pll_enable()  local
2903 	enum pipe pipe = intel_crtc->pipe;  in chv_dp_pre_pll_enable()
2905 		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);  in chv_dp_pre_pll_enable()
2953 	if (intel_crtc->config->lane_count > 2) {  in chv_dp_pre_pll_enable()
3152 	struct intel_crtc *intel_crtc =  in vlv_signal_levels()  local
3158 	int pipe = intel_crtc->pipe;  in vlv_signal_levels()
3258 	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);  in chv_signal_levels()  local
3262 	enum pipe pipe = intel_crtc->pipe;  in chv_signal_levels()
3344 	if (intel_crtc->config->lane_count > 2) {  in chv_signal_levels()
3357 	if (intel_crtc->config->lane_count > 2) {  in chv_signal_levels()
3365 	for (i = 0; i < intel_crtc->config->lane_count; i++) {  in chv_signal_levels()
3373 	for (i = 0; i < intel_crtc->config->lane_count; i++) {  in chv_signal_levels()
3396 	for (i = 0; i < intel_crtc->config->lane_count; i++) {  in chv_signal_levels()
3410 	if (intel_crtc->config->lane_count > 2) {  in chv_signal_levels()
3898 	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);  in intel_dp_link_down()
4085 	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);  in intel_dp_sink_crc_stop()  local
4104 	hsw_enable_ips(intel_crtc);  in intel_dp_sink_crc_stop()
4111 	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);  in intel_dp_sink_crc_start()  local
4132 	hsw_disable_ips(intel_crtc);  in intel_dp_sink_crc_start()
4136 		hsw_enable_ips(intel_crtc);  in intel_dp_sink_crc_start()
4148 	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);  in intel_dp_sink_crc()  local
4159 		intel_wait_for_vblank(dev, intel_crtc->pipe);  in intel_dp_sink_crc()
5497 	struct intel_crtc *intel_crtc = NULL;  in intel_dp_set_drrs_state()  local
5517 	intel_crtc = to_intel_crtc(encoder->base.crtc);  in intel_dp_set_drrs_state()
5519 	if (!intel_crtc) {  in intel_dp_set_drrs_state()
5524 	config = intel_crtc->config;  in intel_dp_set_drrs_state()
5541 	if (!intel_crtc->active) {  in intel_dp_set_drrs_state()
5549 			intel_dp_set_m_n(intel_crtc, M1_N1);  in intel_dp_set_drrs_state()
5552 			intel_dp_set_m_n(intel_crtc, M2_N2);  in intel_dp_set_drrs_state()
5559 		u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);  in intel_dp_set_drrs_state()
5594 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_edp_drrs_enable()  local
5596 	if (!intel_crtc->config->has_drrs) {  in intel_edp_drrs_enable()
5626 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in intel_edp_drrs_disable()  local
5628 	if (!intel_crtc->config->has_drrs)  in intel_edp_drrs_disable()