1112 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)  in skl_edp_set_pll_config()  argument
1116 	memset(&pipe_config->dpll_hw_state, 0,  in skl_edp_set_pll_config()
1117 	       sizeof(pipe_config->dpll_hw_state));  in skl_edp_set_pll_config()
1119 	pipe_config->ddi_pll_sel = SKL_DPLL0;  in skl_edp_set_pll_config()
1120 	pipe_config->dpll_hw_state.cfgcr1 = 0;  in skl_edp_set_pll_config()
1121 	pipe_config->dpll_hw_state.cfgcr2 = 0;  in skl_edp_set_pll_config()
1124 	switch (pipe_config->port_clock / 2) {  in skl_edp_set_pll_config()
1154 	pipe_config->dpll_hw_state.ctrl1 = ctrl1;  in skl_edp_set_pll_config()
1158 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)  in hsw_dp_set_ddi_pll_sel()  argument
1160 	memset(&pipe_config->dpll_hw_state, 0,  in hsw_dp_set_ddi_pll_sel()
1161 	       sizeof(pipe_config->dpll_hw_state));  in hsw_dp_set_ddi_pll_sel()
1163 	switch (pipe_config->port_clock / 2) {  in hsw_dp_set_ddi_pll_sel()
1165 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;  in hsw_dp_set_ddi_pll_sel()
1168 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;  in hsw_dp_set_ddi_pll_sel()
1171 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;  in hsw_dp_set_ddi_pll_sel()
1227 		   struct intel_crtc_state *pipe_config)  in intel_dp_set_clock()  argument
1249 			if (pipe_config->port_clock == divisor[i].clock) {  in intel_dp_set_clock()
1250 				pipe_config->dpll = divisor[i].dpll;  in intel_dp_set_clock()
1251 				pipe_config->clock_set = true;  in intel_dp_set_clock()
1380 			struct intel_crtc_state *pipe_config)  in intel_dp_compute_config()  argument
1384 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;  in intel_dp_compute_config()
1387 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);  in intel_dp_compute_config()
1409 		pipe_config->has_pch_encoder = true;  in intel_dp_compute_config()
1411 	pipe_config->has_dp_encoder = true;  in intel_dp_compute_config()
1412 	pipe_config->has_drrs = false;  in intel_dp_compute_config()
1413 	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;  in intel_dp_compute_config()
1421 			ret = skl_update_scaler_crtc(pipe_config);  in intel_dp_compute_config()
1427 			intel_gmch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1430 			intel_pch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1444 	bpp = pipe_config->pipe_bpp;  in intel_dp_compute_config()
1495 		pipe_config->limited_color_range =  in intel_dp_compute_config()
1498 		pipe_config->limited_color_range =  in intel_dp_compute_config()
1502 	pipe_config->lane_count = lane_count;  in intel_dp_compute_config()
1504 	pipe_config->pipe_bpp = bpp;  in intel_dp_compute_config()
1505 	pipe_config->port_clock = common_rates[clock];  in intel_dp_compute_config()
1507 	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,  in intel_dp_compute_config()
1511 		      link_bw, rate_select, pipe_config->lane_count,  in intel_dp_compute_config()
1512 		      pipe_config->port_clock, bpp);  in intel_dp_compute_config()
1518 			       pipe_config->port_clock,  in intel_dp_compute_config()
1519 			       &pipe_config->dp_m_n);  in intel_dp_compute_config()
1523 			pipe_config->has_drrs = true;  in intel_dp_compute_config()
1526 				pipe_config->port_clock,  in intel_dp_compute_config()
1527 				&pipe_config->dp_m2_n2);  in intel_dp_compute_config()
1531 		skl_edp_set_pll_config(pipe_config);  in intel_dp_compute_config()
1535 		hsw_dp_set_ddi_pll_sel(pipe_config);  in intel_dp_compute_config()
1537 		intel_dp_set_clock(encoder, pipe_config);  in intel_dp_compute_config()
1574 			      const struct intel_crtc_state *pipe_config)  in intel_dp_set_link_params()  argument
1576 	intel_dp->link_rate = pipe_config->port_clock;  in intel_dp_set_link_params()
1577 	intel_dp->lane_count = pipe_config->lane_count;  in intel_dp_set_link_params()
2272 				struct intel_crtc_state *pipe_config)  in intel_dp_get_config()  argument
2284 	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;  in intel_dp_get_config()
2310 	pipe_config->base.adjusted_mode.flags |= flags;  in intel_dp_get_config()
2314 		pipe_config->limited_color_range = true;  in intel_dp_get_config()
2316 	pipe_config->has_dp_encoder = true;  in intel_dp_get_config()
2318 	pipe_config->lane_count =  in intel_dp_get_config()
2321 	intel_dp_get_m_n(crtc, pipe_config);  in intel_dp_get_config()
2325 			pipe_config->port_clock = 162000;  in intel_dp_get_config()
2327 			pipe_config->port_clock = 270000;  in intel_dp_get_config()
2330 	dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in intel_dp_get_config()
2331 					    &pipe_config->dp_m_n);  in intel_dp_get_config()
2334 		ironlake_check_encoder_dotclock(pipe_config, dotclock);  in intel_dp_get_config()
2336 	pipe_config->base.adjusted_mode.crtc_clock = dotclock;  in intel_dp_get_config()
2339 	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {  in intel_dp_get_config()
2354 			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);  in intel_dp_get_config()
2355 		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;  in intel_dp_get_config()