74 	I915_WRITE(FBC_CONTROL, fbc_ctl);  in i8xx_fbc_disable()
109 		I915_WRITE(FBC_TAG(i), 0);  in i8xx_fbc_enable()
117 		I915_WRITE(FBC_CONTROL2, fbc_ctl2);  in i8xx_fbc_enable()
118 		I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc));  in i8xx_fbc_enable()
129 	I915_WRITE(FBC_CONTROL, fbc_ctl);  in i8xx_fbc_enable()
156 	I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc));  in g4x_fbc_enable()
159 	I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);  in g4x_fbc_enable()
174 		I915_WRITE(DPFC_CONTROL, dpfc_ctl);  in g4x_fbc_disable()
187 	I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);  in intel_fbc_nuke()
223 	I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset);  in ilk_fbc_enable()
224 	I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);  in ilk_fbc_enable()
226 	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);  in ilk_fbc_enable()
229 		I915_WRITE(SNB_DPFC_CTL_SA,  in ilk_fbc_enable()
231 		I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset);  in ilk_fbc_enable()
249 		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);  in ilk_fbc_disable()
297 		I915_WRITE(ILK_DISPLAY_CHICKEN1,  in gen7_fbc_enable()
302 		I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe),  in gen7_fbc_enable()
307 	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);  in gen7_fbc_enable()
309 	I915_WRITE(SNB_DPFC_CTL_SA,  in gen7_fbc_enable()
311 	I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc));  in gen7_fbc_enable()
638 		I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);  in intel_fbc_alloc_cfb()
640 		I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);  in intel_fbc_alloc_cfb()
653 		I915_WRITE(FBC_CFB_BASE,  in intel_fbc_alloc_cfb()
655 		I915_WRITE(FBC_LL_BASE,  in intel_fbc_alloc_cfb()
1121 		I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);  in intel_fbc_init()