91 		I915_WRITE(RING_MODE_GEN7(ring), irqs);  in direct_interrupts_to_host()
94 	I915_WRITE(GUC_BCS_RCS_IER, 0);  in direct_interrupts_to_host()
95 	I915_WRITE(GUC_VCS2_VCS1_IER, 0);  in direct_interrupts_to_host()
96 	I915_WRITE(GUC_WD_VECS_IER, 0);  in direct_interrupts_to_host()
108 		I915_WRITE(RING_MODE_GEN7(ring), irqs);  in direct_interrupts_to_guc()
114 	I915_WRITE(GUC_BCS_RCS_IER, ~irqs);  in direct_interrupts_to_guc()
115 	I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);  in direct_interrupts_to_guc()
116 	I915_WRITE(GUC_WD_VECS_IER, ~irqs);  in direct_interrupts_to_guc()
183 	I915_WRITE(SOFT_SCRATCH(0), 0);  in set_guc_init_params()
186 		I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);  in set_guc_init_params()
246 	I915_WRITE(DMA_COPY_SIZE, ucode_size);  in guc_ucode_xfer_dma()
251 		I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);  in guc_ucode_xfer_dma()
255 	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));  in guc_ucode_xfer_dma()
256 	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);  in guc_ucode_xfer_dma()
262 	I915_WRITE(DMA_ADDR_1_LOW, 0x2000);  in guc_ucode_xfer_dma()
263 	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);  in guc_ucode_xfer_dma()
266 	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));  in guc_ucode_xfer_dma()
313 	I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);  in guc_ucode_xfer()
318 	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);  in guc_ucode_xfer()
319 	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);  in guc_ucode_xfer()
322 	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);  in guc_ucode_xfer()
327 		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &  in guc_ucode_xfer()
332 	I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);  in guc_ucode_xfer()
335 		I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);  in guc_ucode_xfer()
337 		I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);  in guc_ucode_xfer()
341 		I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |  in guc_ucode_xfer()
345 		I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);  in guc_ucode_xfer()