Lines Matching refs:I915_WRITE
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
76 I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950)); in bxt_init_clock_gating()
295 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); in intel_set_memory_cxsr()
299 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in intel_set_memory_cxsr()
304 I915_WRITE(DSPFW3, val); in intel_set_memory_cxsr()
309 I915_WRITE(FW_BLC_SELF, val); in intel_set_memory_cxsr()
314 I915_WRITE(INSTPM, val); in intel_set_memory_cxsr()
651 I915_WRITE(DSPFW1, reg); in pineview_update_wm()
661 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
670 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
679 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
833 I915_WRITE(VLV_DDL(pipe), in vlv_write_wm_values()
839 I915_WRITE(DSPFW1, in vlv_write_wm_values()
844 I915_WRITE(DSPFW2, in vlv_write_wm_values()
848 I915_WRITE(DSPFW3, in vlv_write_wm_values()
852 I915_WRITE(DSPFW7_CHV, in vlv_write_wm_values()
855 I915_WRITE(DSPFW8_CHV, in vlv_write_wm_values()
858 I915_WRITE(DSPFW9_CHV, in vlv_write_wm_values()
861 I915_WRITE(DSPHOWM, in vlv_write_wm_values()
873 I915_WRITE(DSPFW7, in vlv_write_wm_values()
876 I915_WRITE(DSPHOWM, in vlv_write_wm_values()
887 I915_WRITE(DSPFW4, 0); in vlv_write_wm_values()
888 I915_WRITE(DSPFW5, 0); in vlv_write_wm_values()
889 I915_WRITE(DSPFW6, 0); in vlv_write_wm_values()
890 I915_WRITE(DSPHOWM1, 0); in vlv_write_wm_values()
1219 I915_WRITE(DSPARB, dsparb); in vlv_pipe_set_fifo_size()
1220 I915_WRITE(DSPARB2, dsparb2); in vlv_pipe_set_fifo_size()
1236 I915_WRITE(DSPARB, dsparb); in vlv_pipe_set_fifo_size()
1237 I915_WRITE(DSPARB2, dsparb2); in vlv_pipe_set_fifo_size()
1253 I915_WRITE(DSPARB3, dsparb3); in vlv_pipe_set_fifo_size()
1254 I915_WRITE(DSPARB2, dsparb2); in vlv_pipe_set_fifo_size()
1405 I915_WRITE(DSPFW1, in g4x_update_wm()
1410 I915_WRITE(DSPFW2, in g4x_update_wm()
1414 I915_WRITE(DSPFW3, in g4x_update_wm()
1481 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | in i965_update_wm()
1485 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | in i965_update_wm()
1488 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); in i965_update_wm()
1603 I915_WRITE(FW_BLC_SELF, in i9xx_update_wm()
1606 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); in i9xx_update_wm()
1619 I915_WRITE(FW_BLC, fwater_lo); in i9xx_update_wm()
1620 I915_WRITE(FW_BLC2, fwater_hi); in i9xx_update_wm()
1649 I915_WRITE(FW_BLC, fwater_lo); in i845_update_wm()
2655 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); in _ilk_disable_lp_wm()
2660 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); in _ilk_disable_lp_wm()
2665 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); in _ilk_disable_lp_wm()
2696 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); in ilk_write_wm_values()
2698 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); in ilk_write_wm_values()
2700 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); in ilk_write_wm_values()
2703 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); in ilk_write_wm_values()
2705 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); in ilk_write_wm_values()
2707 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); in ilk_write_wm_values()
2716 I915_WRITE(WM_MISC, val); in ilk_write_wm_values()
2723 I915_WRITE(DISP_ARB_CTL2, val); in ilk_write_wm_values()
2733 I915_WRITE(DISP_ARB_CTL, val); in ilk_write_wm_values()
2738 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); in ilk_write_wm_values()
2742 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); in ilk_write_wm_values()
2744 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); in ilk_write_wm_values()
2748 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); in ilk_write_wm_values()
2750 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); in ilk_write_wm_values()
2752 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); in ilk_write_wm_values()
3367 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); in skl_ddb_entry_write()
3369 I915_WRITE(reg, 0); in skl_ddb_entry_write()
3385 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); in skl_write_wm_values()
3389 I915_WRITE(PLANE_WM(pipe, i, level), in skl_write_wm_values()
3391 I915_WRITE(CUR_WM(pipe, level), in skl_write_wm_values()
3395 I915_WRITE(PLANE_WM_TRANS(pipe, i), in skl_write_wm_values()
3397 I915_WRITE(CUR_WM_TRANS(pipe), in skl_write_wm_values()
3446 I915_WRITE(PLANE_SURF(pipe, plane), in skl_wm_flush_pipe()
3449 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); in skl_wm_flush_pipe()
4212 I915_WRITE(RCUPEI, 100000); in ironlake_enable_drps()
4213 I915_WRITE(RCDNEI, 100000); in ironlake_enable_drps()
4216 I915_WRITE(RCBMAXAVG, 90000); in ironlake_enable_drps()
4217 I915_WRITE(RCBMINAVG, 80000); in ironlake_enable_drps()
4219 I915_WRITE(MEMIHYST, 1); in ironlake_enable_drps()
4240 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); in ironlake_enable_drps()
4246 I915_WRITE(VIDSTART, vstart); in ironlake_enable_drps()
4250 I915_WRITE(MEMMODECTL, rgvmodectl); in ironlake_enable_drps()
4277 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); in ironlake_disable_drps()
4278 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); in ironlake_disable_drps()
4279 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); in ironlake_disable_drps()
4280 I915_WRITE(DEIIR, DE_PCU_EVENT); in ironlake_disable_drps()
4281 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); in ironlake_disable_drps()
4287 I915_WRITE(MEMSWCTL, rgvswctl); in ironlake_disable_drps()
4393 I915_WRITE(GEN6_RP_UP_EI, in gen6_set_rps_thresholds()
4395 I915_WRITE(GEN6_RP_UP_THRESHOLD, in gen6_set_rps_thresholds()
4398 I915_WRITE(GEN6_RP_DOWN_EI, in gen6_set_rps_thresholds()
4400 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, in gen6_set_rps_thresholds()
4403 I915_WRITE(GEN6_RP_CONTROL, in gen6_set_rps_thresholds()
4455 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
4458 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
4461 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
4470 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); in gen6_set_rps()
4471 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); in gen6_set_rps()
4491 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); in valleyview_set_rps()
4530 I915_WRITE(GEN6_PMINTRMSK, in gen6_rps_busy()
4547 I915_WRITE(GEN6_PMINTRMSK, in gen6_rps_idle()
4606 I915_WRITE(GEN6_RC_CONTROL, 0); in gen9_disable_rc6()
4613 I915_WRITE(GEN9_PG_ENABLE, 0); in gen9_disable_rps()
4620 I915_WRITE(GEN6_RC_CONTROL, 0); in gen6_disable_rc6()
4627 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); in gen6_disable_rps()
4634 I915_WRITE(GEN6_RC_CONTROL, 0); in cherryview_disable_rc6()
4645 I915_WRITE(GEN6_RC_CONTROL, 0); in valleyview_disable_rc6()
4784 I915_WRITE(GEN6_RC_VIDEO_FREQ, in gen9_enable_rps()
4788 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, in gen9_enable_rps()
4791 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); in gen9_enable_rps()
4810 I915_WRITE(GEN6_RC_STATE, 0); in gen9_enable_rc6()
4817 I915_WRITE(GEN6_RC_CONTROL, 0); in gen9_enable_rc6()
4823 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); in gen9_enable_rc6()
4825 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); in gen9_enable_rc6()
4826 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen9_enable_rc6()
4827 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen9_enable_rc6()
4829 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in gen9_enable_rc6()
4832 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); in gen9_enable_rc6()
4834 I915_WRITE(GEN6_RC_SLEEP, 0); in gen9_enable_rc6()
4837 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); in gen9_enable_rc6()
4838 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); in gen9_enable_rc6()
4849 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ in gen9_enable_rc6()
4850 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen9_enable_rc6()
4854 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ in gen9_enable_rc6()
4855 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen9_enable_rc6()
4866 I915_WRITE(GEN9_PG_ENABLE, 0); in gen9_enable_rc6()
4868 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? in gen9_enable_rc6()
4883 I915_WRITE(GEN6_RC_STATE, 0); in gen8_enable_rps()
4890 I915_WRITE(GEN6_RC_CONTROL, 0); in gen8_enable_rps()
4896 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); in gen8_enable_rps()
4897 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen8_enable_rps()
4898 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen8_enable_rps()
4900 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in gen8_enable_rps()
4901 I915_WRITE(GEN6_RC_SLEEP, 0); in gen8_enable_rps()
4903 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ in gen8_enable_rps()
4905 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ in gen8_enable_rps()
4913 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen8_enable_rps()
4917 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen8_enable_rps()
4922 I915_WRITE(GEN6_RPNSWREQ, in gen8_enable_rps()
4924 I915_WRITE(GEN6_RC_VIDEO_FREQ, in gen8_enable_rps()
4927 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ in gen8_enable_rps()
4930 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, in gen8_enable_rps()
4934 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ in gen8_enable_rps()
4935 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ in gen8_enable_rps()
4936 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ in gen8_enable_rps()
4937 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ in gen8_enable_rps()
4939 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in gen8_enable_rps()
4942 I915_WRITE(GEN6_RP_CONTROL, in gen8_enable_rps()
4975 I915_WRITE(GEN6_RC_STATE, 0); in gen6_enable_rps()
4980 I915_WRITE(GTFIFODBG, gtfifodbg); in gen6_enable_rps()
4989 I915_WRITE(GEN6_RC_CONTROL, 0); in gen6_enable_rps()
4991 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); in gen6_enable_rps()
4992 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); in gen6_enable_rps()
4993 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); in gen6_enable_rps()
4994 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); in gen6_enable_rps()
4995 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); in gen6_enable_rps()
4998 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in gen6_enable_rps()
5000 I915_WRITE(GEN6_RC_SLEEP, 0); in gen6_enable_rps()
5001 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); in gen6_enable_rps()
5003 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); in gen6_enable_rps()
5005 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); in gen6_enable_rps()
5006 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); in gen6_enable_rps()
5007 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ in gen6_enable_rps()
5025 I915_WRITE(GEN6_RC_CONTROL, in gen6_enable_rps()
5031 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); in gen6_enable_rps()
5032 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in gen6_enable_rps()
5288 I915_WRITE(VLV_PCBR, pctx_paddr); in cherryview_setup_pctx()
5334 I915_WRITE(VLV_PCBR, pctx_paddr); in valleyview_setup_pctx()
5490 I915_WRITE(GTFIFODBG, gtfifodbg); in cherryview_enable_rps()
5500 I915_WRITE(GEN6_RC_CONTROL, 0); in cherryview_enable_rps()
5503 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); in cherryview_enable_rps()
5504 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in cherryview_enable_rps()
5505 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in cherryview_enable_rps()
5508 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in cherryview_enable_rps()
5509 I915_WRITE(GEN6_RC_SLEEP, 0); in cherryview_enable_rps()
5512 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); in cherryview_enable_rps()
5515 I915_WRITE(VLV_COUNTER_CONTROL, in cherryview_enable_rps()
5528 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); in cherryview_enable_rps()
5531 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); in cherryview_enable_rps()
5532 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); in cherryview_enable_rps()
5533 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); in cherryview_enable_rps()
5534 I915_WRITE(GEN6_RP_UP_EI, 66000); in cherryview_enable_rps()
5535 I915_WRITE(GEN6_RP_DOWN_EI, 350000); in cherryview_enable_rps()
5537 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in cherryview_enable_rps()
5540 I915_WRITE(GEN6_RP_CONTROL, in cherryview_enable_rps()
5589 I915_WRITE(GTFIFODBG, gtfifodbg); in valleyview_enable_rps()
5596 I915_WRITE(GEN6_RC_CONTROL, 0); in valleyview_enable_rps()
5598 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); in valleyview_enable_rps()
5599 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); in valleyview_enable_rps()
5600 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); in valleyview_enable_rps()
5601 I915_WRITE(GEN6_RP_UP_EI, 66000); in valleyview_enable_rps()
5602 I915_WRITE(GEN6_RP_DOWN_EI, 350000); in valleyview_enable_rps()
5604 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in valleyview_enable_rps()
5606 I915_WRITE(GEN6_RP_CONTROL, in valleyview_enable_rps()
5614 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); in valleyview_enable_rps()
5615 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); in valleyview_enable_rps()
5616 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); in valleyview_enable_rps()
5619 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in valleyview_enable_rps()
5621 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); in valleyview_enable_rps()
5624 I915_WRITE(VLV_COUNTER_CONTROL, in valleyview_enable_rps()
5635 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); in valleyview_enable_rps()
6090 I915_WRITE(ECR, 0); in intel_init_emon()
6094 I915_WRITE(SDEW, 0x15040d00); in intel_init_emon()
6095 I915_WRITE(CSIEW0, 0x007f0000); in intel_init_emon()
6096 I915_WRITE(CSIEW1, 0x1e220004); in intel_init_emon()
6097 I915_WRITE(CSIEW2, 0x04000004); in intel_init_emon()
6100 I915_WRITE(PEW(i), 0); in intel_init_emon()
6102 I915_WRITE(DEW(i), 0); in intel_init_emon()
6127 I915_WRITE(PXW(i), val); in intel_init_emon()
6131 I915_WRITE(OGW0, 0); in intel_init_emon()
6132 I915_WRITE(OGW1, 0); in intel_init_emon()
6133 I915_WRITE(EG0, 0x00007f00); in intel_init_emon()
6134 I915_WRITE(EG1, 0x0000000e); in intel_init_emon()
6135 I915_WRITE(EG2, 0x000e0000); in intel_init_emon()
6136 I915_WRITE(EG3, 0x68000300); in intel_init_emon()
6137 I915_WRITE(EG4, 0x42000000); in intel_init_emon()
6138 I915_WRITE(EG5, 0x00140031); in intel_init_emon()
6139 I915_WRITE(EG6, 0); in intel_init_emon()
6140 I915_WRITE(EG7, 0); in intel_init_emon()
6143 I915_WRITE(PXWL(i), 0); in intel_init_emon()
6146 I915_WRITE(ECR, 0x80000019); in intel_init_emon()
6441 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); in ibx_init_clock_gating()
6450 I915_WRITE(DSPCNTR(pipe), in g4x_disable_trickle_feed()
6454 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); in g4x_disable_trickle_feed()
6463 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
6464 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
6465 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
6486 I915_WRITE(PCH_3DCGDIS0, in ironlake_init_clock_gating()
6489 I915_WRITE(PCH_3DCGDIS1, in ironlake_init_clock_gating()
6499 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ironlake_init_clock_gating()
6503 I915_WRITE(DISP_ARB_CTL, in ironlake_init_clock_gating()
6518 I915_WRITE(ILK_DISPLAY_CHICKEN1, in ironlake_init_clock_gating()
6521 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ironlake_init_clock_gating()
6526 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); in ironlake_init_clock_gating()
6528 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ironlake_init_clock_gating()
6531 I915_WRITE(_3D_CHICKEN2, in ironlake_init_clock_gating()
6536 I915_WRITE(CACHE_MODE_0, in ironlake_init_clock_gating()
6540 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ironlake_init_clock_gating()
6558 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | in cpt_init_clock_gating()
6561 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | in cpt_init_clock_gating()
6575 I915_WRITE(TRANS_CHICKEN2(pipe), val); in cpt_init_clock_gating()
6579 I915_WRITE(TRANS_CHICKEN1(pipe), in cpt_init_clock_gating()
6600 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); in gen6_init_clock_gating()
6602 I915_WRITE(ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
6607 I915_WRITE(_3D_CHICKEN, in gen6_init_clock_gating()
6611 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in gen6_init_clock_gating()
6621 I915_WRITE(GEN6_GT_MODE, in gen6_init_clock_gating()
6626 I915_WRITE(CACHE_MODE_0, in gen6_init_clock_gating()
6629 I915_WRITE(GEN6_UCGCTL1, in gen6_init_clock_gating()
6647 I915_WRITE(GEN6_UCGCTL2, in gen6_init_clock_gating()
6652 I915_WRITE(_3D_CHICKEN3, in gen6_init_clock_gating()
6660 I915_WRITE(_3D_CHICKEN3, in gen6_init_clock_gating()
6674 I915_WRITE(ILK_DISPLAY_CHICKEN1, in gen6_init_clock_gating()
6677 I915_WRITE(ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
6680 I915_WRITE(ILK_DSPCLK_GATE_D, in gen6_init_clock_gating()
6707 I915_WRITE(GEN7_FF_THREAD_MODE, reg); in gen7_setup_fixed_func_scheduler()
6719 I915_WRITE(SOUTH_DSPCLK_GATE_D, in lpt_init_clock_gating()
6724 I915_WRITE(TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
6737 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); in lpt_suspend_hw()
6750 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in broadwell_init_clock_gating()
6753 I915_WRITE(CHICKEN_PAR1_1, in broadwell_init_clock_gating()
6758 I915_WRITE(CHICKEN_PIPESL_1(pipe), in broadwell_init_clock_gating()
6765 I915_WRITE(GEN7_FF_THREAD_MODE, in broadwell_init_clock_gating()
6769 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, in broadwell_init_clock_gating()
6773 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in broadwell_init_clock_gating()
6781 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in broadwell_init_clock_gating()
6782 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); in broadwell_init_clock_gating()
6789 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in broadwell_init_clock_gating()
6796 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); in broadwell_init_clock_gating()
6808 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); in haswell_init_clock_gating()
6809 I915_WRITE(HSW_ROW_CHICKEN3, in haswell_init_clock_gating()
6813 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in haswell_init_clock_gating()
6818 I915_WRITE(GEN7_FF_THREAD_MODE, in haswell_init_clock_gating()
6822 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in haswell_init_clock_gating()
6825 I915_WRITE(CACHE_MODE_0_GEN7, in haswell_init_clock_gating()
6829 I915_WRITE(CACHE_MODE_1, in haswell_init_clock_gating()
6840 I915_WRITE(GEN7_GT_MODE, in haswell_init_clock_gating()
6844 I915_WRITE(HALF_SLICE_CHICKEN3, in haswell_init_clock_gating()
6848 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in haswell_init_clock_gating()
6851 I915_WRITE(CHICKEN_PAR1_1, in haswell_init_clock_gating()
6864 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); in ivybridge_init_clock_gating()
6867 I915_WRITE(_3D_CHICKEN3, in ivybridge_init_clock_gating()
6871 I915_WRITE(IVB_CHICKEN3, in ivybridge_init_clock_gating()
6877 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, in ivybridge_init_clock_gating()
6881 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ivybridge_init_clock_gating()
6884 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, in ivybridge_init_clock_gating()
6888 I915_WRITE(GEN7_L3CNTLREG1, in ivybridge_init_clock_gating()
6890 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, in ivybridge_init_clock_gating()
6893 I915_WRITE(GEN7_ROW_CHICKEN2, in ivybridge_init_clock_gating()
6897 I915_WRITE(GEN7_ROW_CHICKEN2, in ivybridge_init_clock_gating()
6899 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, in ivybridge_init_clock_gating()
6904 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in ivybridge_init_clock_gating()
6911 I915_WRITE(GEN6_UCGCTL2, in ivybridge_init_clock_gating()
6915 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in ivybridge_init_clock_gating()
6925 I915_WRITE(CACHE_MODE_0_GEN7, in ivybridge_init_clock_gating()
6930 I915_WRITE(CACHE_MODE_1, in ivybridge_init_clock_gating()
6941 I915_WRITE(GEN7_GT_MODE, in ivybridge_init_clock_gating()
6947 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); in ivybridge_init_clock_gating()
6968 I915_WRITE(DSPCLK_GATE_D, val); in vlv_init_display_clock_gating()
6973 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); in vlv_init_display_clock_gating()
6974 I915_WRITE(CBR1_VLV, 0); in vlv_init_display_clock_gating()
6984 I915_WRITE(_3D_CHICKEN3, in valleyview_init_clock_gating()
6988 I915_WRITE(IVB_CHICKEN3, in valleyview_init_clock_gating()
6994 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, in valleyview_init_clock_gating()
6999 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in valleyview_init_clock_gating()
7002 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in valleyview_init_clock_gating()
7006 I915_WRITE(GEN7_ROW_CHICKEN2, in valleyview_init_clock_gating()
7010 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in valleyview_init_clock_gating()
7020 I915_WRITE(GEN6_UCGCTL2, in valleyview_init_clock_gating()
7026 I915_WRITE(GEN7_UCGCTL4, in valleyview_init_clock_gating()
7033 I915_WRITE(CACHE_MODE_1, in valleyview_init_clock_gating()
7044 I915_WRITE(GEN7_GT_MODE, in valleyview_init_clock_gating()
7051 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); in valleyview_init_clock_gating()
7058 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); in valleyview_init_clock_gating()
7069 I915_WRITE(GEN7_FF_THREAD_MODE, in cherryview_init_clock_gating()
7074 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, in cherryview_init_clock_gating()
7078 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | in cherryview_init_clock_gating()
7082 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in cherryview_init_clock_gating()
7089 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); in cherryview_init_clock_gating()
7097 I915_WRITE(RENCLK_GATE_D1, 0); in g4x_init_clock_gating()
7098 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | in g4x_init_clock_gating()
7101 I915_WRITE(RAMCLK_GATE_D, 0); in g4x_init_clock_gating()
7107 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); in g4x_init_clock_gating()
7110 I915_WRITE(CACHE_MODE_0, in g4x_init_clock_gating()
7114 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in g4x_init_clock_gating()
7123 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); in crestline_init_clock_gating()
7124 I915_WRITE(RENCLK_GATE_D2, 0); in crestline_init_clock_gating()
7125 I915_WRITE(DSPCLK_GATE_D, 0); in crestline_init_clock_gating()
7126 I915_WRITE(RAMCLK_GATE_D, 0); in crestline_init_clock_gating()
7128 I915_WRITE(MI_ARB_STATE, in crestline_init_clock_gating()
7132 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in crestline_init_clock_gating()
7139 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | in broadwater_init_clock_gating()
7144 I915_WRITE(RENCLK_GATE_D2, 0); in broadwater_init_clock_gating()
7145 I915_WRITE(MI_ARB_STATE, in broadwater_init_clock_gating()
7149 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in broadwater_init_clock_gating()
7159 I915_WRITE(D_STATE, dstate); in gen3_init_clock_gating()
7162 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); in gen3_init_clock_gating()
7165 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); in gen3_init_clock_gating()
7168 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
7171 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); in gen3_init_clock_gating()
7173 I915_WRITE(MI_ARB_STATE, in gen3_init_clock_gating()
7181 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); in i85x_init_clock_gating()
7184 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | in i85x_init_clock_gating()
7187 I915_WRITE(MEM_MODE, in i85x_init_clock_gating()
7195 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); in i830_init_clock_gating()
7197 I915_WRITE(MEM_MODE, in i830_init_clock_gating()
7330 I915_WRITE(GEN6_PCODE_DATA, *val); in sandybridge_pcode_read()
7331 I915_WRITE(GEN6_PCODE_DATA1, 0); in sandybridge_pcode_read()
7332 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); in sandybridge_pcode_read()
7341 I915_WRITE(GEN6_PCODE_DATA, 0); in sandybridge_pcode_read()
7355 I915_WRITE(GEN6_PCODE_DATA, val); in sandybridge_pcode_write()
7356 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); in sandybridge_pcode_write()
7364 I915_WRITE(GEN6_PCODE_DATA, 0); in sandybridge_pcode_write()