Lines Matching refs:rps
252 mutex_lock(&dev_priv->rps.hw_lock); in chv_set_memory_dvfs()
267 mutex_unlock(&dev_priv->rps.hw_lock); in chv_set_memory_dvfs()
274 mutex_lock(&dev_priv->rps.hw_lock); in chv_set_memory_pm5()
283 mutex_unlock(&dev_priv->rps.hw_lock); in chv_set_memory_pm5()
2068 mutex_lock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
2072 mutex_unlock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
2089 mutex_lock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
2093 mutex_unlock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
4039 mutex_lock(&dev_priv->rps.hw_lock); in vlv_wm_get_hw_state()
4069 mutex_unlock(&dev_priv->rps.hw_lock); in vlv_wm_get_hw_state()
4309 limits = (dev_priv->rps.max_freq_softlimit) << 23; in intel_rps_limits()
4310 if (val <= dev_priv->rps.min_freq_softlimit) in intel_rps_limits()
4311 limits |= (dev_priv->rps.min_freq_softlimit) << 14; in intel_rps_limits()
4313 limits = dev_priv->rps.max_freq_softlimit << 24; in intel_rps_limits()
4314 if (val <= dev_priv->rps.min_freq_softlimit) in intel_rps_limits()
4315 limits |= dev_priv->rps.min_freq_softlimit << 16; in intel_rps_limits()
4327 new_power = dev_priv->rps.power; in gen6_set_rps_thresholds()
4328 switch (dev_priv->rps.power) { in gen6_set_rps_thresholds()
4330 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4335 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4337 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4342 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
4347 if (val <= dev_priv->rps.min_freq_softlimit) in gen6_set_rps_thresholds()
4349 if (val >= dev_priv->rps.max_freq_softlimit) in gen6_set_rps_thresholds()
4351 if (new_power == dev_priv->rps.power) in gen6_set_rps_thresholds()
4412 dev_priv->rps.power = new_power; in gen6_set_rps_thresholds()
4413 dev_priv->rps.up_threshold = threshold_up; in gen6_set_rps_thresholds()
4414 dev_priv->rps.down_threshold = threshold_down; in gen6_set_rps_thresholds()
4415 dev_priv->rps.last_adj = 0; in gen6_set_rps_thresholds()
4423 if (val > dev_priv->rps.min_freq_softlimit) in gen6_rps_pm_mask()
4425 if (val < dev_priv->rps.max_freq_softlimit) in gen6_rps_pm_mask()
4444 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in gen6_set_rps()
4445 WARN_ON(val > dev_priv->rps.max_freq); in gen6_set_rps()
4446 WARN_ON(val < dev_priv->rps.min_freq); in gen6_set_rps()
4451 if (val != dev_priv->rps.cur_freq) { in gen6_set_rps()
4475 dev_priv->rps.cur_freq = val; in gen6_set_rps()
4483 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in valleyview_set_rps()
4484 WARN_ON(val > dev_priv->rps.max_freq); in valleyview_set_rps()
4485 WARN_ON(val < dev_priv->rps.min_freq); in valleyview_set_rps()
4493 if (val != dev_priv->rps.cur_freq) { in valleyview_set_rps()
4499 dev_priv->rps.cur_freq = val; in valleyview_set_rps()
4512 u32 val = dev_priv->rps.idle_freq; in vlv_set_rps_idle()
4514 if (dev_priv->rps.cur_freq <= val) in vlv_set_rps_idle()
4526 mutex_lock(&dev_priv->rps.hw_lock); in gen6_rps_busy()
4527 if (dev_priv->rps.enabled) { in gen6_rps_busy()
4531 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); in gen6_rps_busy()
4533 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_rps_busy()
4540 mutex_lock(&dev_priv->rps.hw_lock); in gen6_rps_idle()
4541 if (dev_priv->rps.enabled) { in gen6_rps_idle()
4545 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); in gen6_rps_idle()
4546 dev_priv->rps.last_adj = 0; in gen6_rps_idle()
4550 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_rps_idle()
4552 spin_lock(&dev_priv->rps.client_lock); in gen6_rps_idle()
4553 while (!list_empty(&dev_priv->rps.clients)) in gen6_rps_idle()
4554 list_del_init(dev_priv->rps.clients.next); in gen6_rps_idle()
4555 spin_unlock(&dev_priv->rps.client_lock); in gen6_rps_idle()
4559 struct intel_rps_client *rps, in gen6_rps_boost() argument
4566 dev_priv->rps.enabled && in gen6_rps_boost()
4567 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) in gen6_rps_boost()
4573 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) in gen6_rps_boost()
4574 rps = NULL; in gen6_rps_boost()
4576 spin_lock(&dev_priv->rps.client_lock); in gen6_rps_boost()
4577 if (rps == NULL || list_empty(&rps->link)) { in gen6_rps_boost()
4579 if (dev_priv->rps.interrupts_enabled) { in gen6_rps_boost()
4580 dev_priv->rps.client_boost = true; in gen6_rps_boost()
4581 queue_work(dev_priv->wq, &dev_priv->rps.work); in gen6_rps_boost()
4585 if (rps != NULL) { in gen6_rps_boost()
4586 list_add(&rps->link, &dev_priv->rps.clients); in gen6_rps_boost()
4587 rps->boosts++; in gen6_rps_boost()
4589 dev_priv->rps.boosts++; in gen6_rps_boost()
4591 spin_unlock(&dev_priv->rps.client_lock); in gen6_rps_boost()
4711 dev_priv->rps.cur_freq = 0; in gen6_init_rps_frequencies()
4715 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
4716 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; in gen6_init_rps_frequencies()
4717 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
4720 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
4721 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; in gen6_init_rps_frequencies()
4722 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
4726 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; in gen6_init_rps_frequencies()
4728 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; in gen6_init_rps_frequencies()
4734 dev_priv->rps.efficient_freq = in gen6_init_rps_frequencies()
4737 dev_priv->rps.min_freq, in gen6_init_rps_frequencies()
4738 dev_priv->rps.max_freq); in gen6_init_rps_frequencies()
4744 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4745 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4746 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4747 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4748 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4751 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in gen6_init_rps_frequencies()
4754 if (dev_priv->rps.max_freq_softlimit == 0) in gen6_init_rps_frequencies()
4755 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; in gen6_init_rps_frequencies()
4757 if (dev_priv->rps.min_freq_softlimit == 0) { in gen6_init_rps_frequencies()
4759 dev_priv->rps.min_freq_softlimit = in gen6_init_rps_frequencies()
4760 max_t(int, dev_priv->rps.efficient_freq, in gen6_init_rps_frequencies()
4763 dev_priv->rps.min_freq_softlimit = in gen6_init_rps_frequencies()
4764 dev_priv->rps.min_freq; in gen6_init_rps_frequencies()
4785 GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); in gen9_enable_rps()
4796 dev_priv->rps.power = HIGH_POWER; /* force a reset */ in gen9_enable_rps()
4797 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); in gen9_enable_rps()
4841 if (!dev_priv->rps.ctx_corrupted && in gen9_enable_rc6()
4908 if (!dev_priv->rps.ctx_corrupted && in gen8_enable_rps()
4923 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); in gen8_enable_rps()
4925 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); in gen8_enable_rps()
4931 dev_priv->rps.max_freq_softlimit << 24 | in gen8_enable_rps()
4932 dev_priv->rps.min_freq_softlimit << 16); in gen8_enable_rps()
4952 dev_priv->rps.power = HIGH_POWER; /* force a reset */ in gen8_enable_rps()
4953 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); in gen8_enable_rps()
4967 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in gen6_enable_rps()
5041 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, in gen6_enable_rps()
5043 dev_priv->rps.max_freq = pcu_mbox & 0xff; in gen6_enable_rps()
5046 dev_priv->rps.power = HIGH_POWER; /* force a reset */ in gen6_enable_rps()
5047 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); in gen6_enable_rps()
5076 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in __gen6_update_ring_freq()
5099 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; in __gen6_update_ring_freq()
5100 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; in __gen6_update_ring_freq()
5102 min_gpu_freq = dev_priv->rps.min_freq; in __gen6_update_ring_freq()
5103 max_gpu_freq = dev_priv->rps.max_freq; in __gen6_update_ring_freq()
5158 mutex_lock(&dev_priv->rps.hw_lock); in gen6_update_ring_freq()
5160 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_update_ring_freq()
5359 mutex_lock(&dev_priv->rps.hw_lock); in valleyview_init_gt_powersave()
5376 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); in valleyview_init_gt_powersave()
5377 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; in valleyview_init_gt_powersave()
5379 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), in valleyview_init_gt_powersave()
5380 dev_priv->rps.max_freq); in valleyview_init_gt_powersave()
5382 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); in valleyview_init_gt_powersave()
5384 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in valleyview_init_gt_powersave()
5385 dev_priv->rps.efficient_freq); in valleyview_init_gt_powersave()
5387 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); in valleyview_init_gt_powersave()
5389 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), in valleyview_init_gt_powersave()
5390 dev_priv->rps.rp1_freq); in valleyview_init_gt_powersave()
5392 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); in valleyview_init_gt_powersave()
5394 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), in valleyview_init_gt_powersave()
5395 dev_priv->rps.min_freq); in valleyview_init_gt_powersave()
5397 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in valleyview_init_gt_powersave()
5400 if (dev_priv->rps.max_freq_softlimit == 0) in valleyview_init_gt_powersave()
5401 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; in valleyview_init_gt_powersave()
5403 if (dev_priv->rps.min_freq_softlimit == 0) in valleyview_init_gt_powersave()
5404 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; in valleyview_init_gt_powersave()
5406 mutex_unlock(&dev_priv->rps.hw_lock); in valleyview_init_gt_powersave()
5416 mutex_lock(&dev_priv->rps.hw_lock); in cherryview_init_gt_powersave()
5432 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); in cherryview_init_gt_powersave()
5433 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; in cherryview_init_gt_powersave()
5435 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), in cherryview_init_gt_powersave()
5436 dev_priv->rps.max_freq); in cherryview_init_gt_powersave()
5438 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); in cherryview_init_gt_powersave()
5440 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in cherryview_init_gt_powersave()
5441 dev_priv->rps.efficient_freq); in cherryview_init_gt_powersave()
5443 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); in cherryview_init_gt_powersave()
5445 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), in cherryview_init_gt_powersave()
5446 dev_priv->rps.rp1_freq); in cherryview_init_gt_powersave()
5449 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; in cherryview_init_gt_powersave()
5451 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), in cherryview_init_gt_powersave()
5452 dev_priv->rps.min_freq); in cherryview_init_gt_powersave()
5454 WARN_ONCE((dev_priv->rps.max_freq | in cherryview_init_gt_powersave()
5455 dev_priv->rps.efficient_freq | in cherryview_init_gt_powersave()
5456 dev_priv->rps.rp1_freq | in cherryview_init_gt_powersave()
5457 dev_priv->rps.min_freq) & 1, in cherryview_init_gt_powersave()
5460 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in cherryview_init_gt_powersave()
5463 if (dev_priv->rps.max_freq_softlimit == 0) in cherryview_init_gt_powersave()
5464 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; in cherryview_init_gt_powersave()
5466 if (dev_priv->rps.min_freq_softlimit == 0) in cherryview_init_gt_powersave()
5467 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; in cherryview_init_gt_powersave()
5469 mutex_unlock(&dev_priv->rps.hw_lock); in cherryview_init_gt_powersave()
5484 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in cherryview_enable_rps()
5561 dev_priv->rps.cur_freq = (val >> 8) & 0xff; in cherryview_enable_rps()
5563 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), in cherryview_enable_rps()
5564 dev_priv->rps.cur_freq); in cherryview_enable_rps()
5567 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in cherryview_enable_rps()
5568 dev_priv->rps.efficient_freq); in cherryview_enable_rps()
5570 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); in cherryview_enable_rps()
5582 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in valleyview_enable_rps()
5651 dev_priv->rps.cur_freq = (val >> 8) & 0xff; in valleyview_enable_rps()
5653 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), in valleyview_enable_rps()
5654 dev_priv->rps.cur_freq); in valleyview_enable_rps()
5657 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in valleyview_enable_rps()
5658 dev_priv->rps.efficient_freq); in valleyview_enable_rps()
5660 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); in valleyview_enable_rps()
5857 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); in __i915_gfx_val()
6165 i915->rps.ctx_corrupted = true; in i915_rc6_ctx_wa_init()
6172 if (i915->rps.ctx_corrupted) { in i915_rc6_ctx_wa_cleanup()
6174 i915->rps.ctx_corrupted = false; in i915_rc6_ctx_wa_cleanup()
6186 if (i915->rps.ctx_corrupted) in i915_rc6_ctx_wa_suspend()
6198 if (!i915->rps.ctx_corrupted) in i915_rc6_ctx_wa_resume()
6207 i915->rps.ctx_corrupted = false; in i915_rc6_ctx_wa_resume()
6227 if (i915->rps.ctx_corrupted) in i915_rc6_ctx_wa_check()
6236 i915->rps.ctx_corrupted = true; in i915_rc6_ctx_wa_check()
6268 flush_delayed_work(&dev_priv->rps.delayed_resume_work); in gen6_suspend_rps()
6310 mutex_lock(&dev_priv->rps.hw_lock); in intel_disable_rc6()
6312 mutex_unlock(&dev_priv->rps.hw_lock); in intel_disable_rc6()
6335 mutex_lock(&dev_priv->rps.hw_lock); in intel_disable_gt_powersave()
6340 dev_priv->rps.enabled = false; in intel_disable_gt_powersave()
6342 mutex_unlock(&dev_priv->rps.hw_lock); in intel_disable_gt_powersave()
6350 rps.delayed_resume_work.work); in intel_gen6_powersave_work()
6353 mutex_lock(&dev_priv->rps.hw_lock); in intel_gen6_powersave_work()
6374 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); in intel_gen6_powersave_work()
6375 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); in intel_gen6_powersave_work()
6377 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); in intel_gen6_powersave_work()
6378 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); in intel_gen6_powersave_work()
6380 dev_priv->rps.enabled = true; in intel_gen6_powersave_work()
6384 mutex_unlock(&dev_priv->rps.hw_lock); in intel_gen6_powersave_work()
6415 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, in intel_enable_gt_powersave()
6429 dev_priv->rps.enabled = false; in intel_reset_gt_powersave()
7323 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in sandybridge_pcode_read()
7348 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in sandybridge_pcode_write()
7501 mutex_init(&dev_priv->rps.hw_lock); in intel_pm_setup()
7502 spin_lock_init(&dev_priv->rps.client_lock); in intel_pm_setup()
7504 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, in intel_pm_setup()
7506 INIT_LIST_HEAD(&dev_priv->rps.clients); in intel_pm_setup()
7507 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); in intel_pm_setup()
7508 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); in intel_pm_setup()