Lines Matching refs:I915_WRITE
90 I915_WRITE(ctl_reg, 0); in intel_psr_write_vsc()
94 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, in intel_psr_write_vsc()
99 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, in intel_psr_write_vsc()
102 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); in intel_psr_write_vsc()
119 I915_WRITE(VLV_VSCSDP(pipe), val); in vlv_psr_setup_vsc()
191 I915_WRITE(aux_data_reg + i, in hsw_psr_enable_sink()
206 I915_WRITE(aux_ctl_reg, val); in hsw_psr_enable_sink()
208 I915_WRITE(aux_ctl_reg, in hsw_psr_enable_sink()
227 I915_WRITE(VLV_PSRCTL(pipe), in vlv_psr_enable_source()
246 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | in vlv_psr_activate()
279 I915_WRITE(EDP_PSR_CTL(dev), val | in hsw_psr_enable_source()
286 I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE | in hsw_psr_enable_source()
407 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | in intel_psr_enable()
454 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); in vlv_psr_disable()
469 I915_WRITE(EDP_PSR_CTL(dev), in hsw_psr_disable()
573 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); in intel_psr_exit()
585 I915_WRITE(VLV_PSRCTL(pipe), val); in intel_psr_exit()
642 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE); in intel_psr_single_frame_update()