Lines Matching refs:gpu_write
44 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
46 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
48 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
50 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
52 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222); in a4xx_enable_hwcg()
54 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222); in a4xx_enable_hwcg()
56 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_SP(i), 0x00000104); in a4xx_enable_hwcg()
58 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_SP(i), 0x00000081); in a4xx_enable_hwcg()
59 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_UCHE, 0x22222222); in a4xx_enable_hwcg()
60 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_UCHE, 0x02222222); in a4xx_enable_hwcg()
61 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL3_UCHE, 0x00000000); in a4xx_enable_hwcg()
62 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL4_UCHE, 0x00000000); in a4xx_enable_hwcg()
63 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_UCHE, 0x00004444); in a4xx_enable_hwcg()
64 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_UCHE, 0x00001112); in a4xx_enable_hwcg()
66 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_RB(i), 0x22222222); in a4xx_enable_hwcg()
71 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i), in a4xx_enable_hwcg()
74 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i), in a4xx_enable_hwcg()
80 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i), in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i), in a4xx_enable_hwcg()
90 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i), in a4xx_enable_hwcg()
94 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222); in a4xx_enable_hwcg()
95 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_GPC, 0x04100104); in a4xx_enable_hwcg()
96 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_GPC, 0x00022222); in a4xx_enable_hwcg()
97 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM, 0x00000022); in a4xx_enable_hwcg()
98 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM, 0x0000010F); in a4xx_enable_hwcg()
99 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM, 0x00000022); in a4xx_enable_hwcg()
100 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM, 0x00222222); in a4xx_enable_hwcg()
101 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00004104); in a4xx_enable_hwcg()
102 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222); in a4xx_enable_hwcg()
103 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_HLSQ , 0x00000000); in a4xx_enable_hwcg()
104 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000); in a4xx_enable_hwcg()
105 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00020000); in a4xx_enable_hwcg()
106 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); in a4xx_enable_hwcg()
107 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0); in a4xx_enable_hwcg()
145 gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F); in a4xx_hw_init()
146 gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4); in a4xx_hw_init()
147 gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001); in a4xx_hw_init()
148 gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818); in a4xx_hw_init()
149 gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018); in a4xx_hw_init()
150 gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818); in a4xx_hw_init()
151 gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018); in a4xx_hw_init()
152 gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); in a4xx_hw_init()
158 gpu_write(gpu, REG_A4XX_RBBM_GPU_BUSY_MASKED, 0xffffffff); in a4xx_hw_init()
161 gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10); in a4xx_hw_init()
162 gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10); in a4xx_hw_init()
165 gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001); in a4xx_hw_init()
168 gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL1, 0xa6ffffff); in a4xx_hw_init()
171 gpu_write(gpu, REG_A4XX_RBBM_RBBM_CTL, 0x00000030); in a4xx_hw_init()
177 gpu_write(gpu, REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL, in a4xx_hw_init()
180 gpu_write(gpu, REG_A4XX_RB_GMEM_BASE_ADDR, in a4xx_hw_init()
184 gpu_write(gpu, REG_A4XX_RBBM_PERFCTR_CTL, 0x01); in a4xx_hw_init()
187 gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000); in a4xx_hw_init()
188 gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000); in a4xx_hw_init()
190 gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) | in a4xx_hw_init()
204 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, val); in a4xx_hw_init()
212 gpu_write(gpu, REG_A4XX_CP_PROTECT_CTRL, 0x00000007); in a4xx_hw_init()
215 gpu_write(gpu, REG_A4XX_CP_PROTECT(0), 0x62000010); in a4xx_hw_init()
216 gpu_write(gpu, REG_A4XX_CP_PROTECT(1), 0x63000020); in a4xx_hw_init()
217 gpu_write(gpu, REG_A4XX_CP_PROTECT(2), 0x64000040); in a4xx_hw_init()
218 gpu_write(gpu, REG_A4XX_CP_PROTECT(3), 0x65000080); in a4xx_hw_init()
219 gpu_write(gpu, REG_A4XX_CP_PROTECT(4), 0x66000100); in a4xx_hw_init()
220 gpu_write(gpu, REG_A4XX_CP_PROTECT(5), 0x64000200); in a4xx_hw_init()
223 gpu_write(gpu, REG_A4XX_CP_PROTECT(6), 0x67000800); in a4xx_hw_init()
224 gpu_write(gpu, REG_A4XX_CP_PROTECT(7), 0x64001600); in a4xx_hw_init()
228 gpu_write(gpu, REG_A4XX_CP_PROTECT(8), 0x60003300); in a4xx_hw_init()
231 gpu_write(gpu, REG_A4XX_CP_PROTECT(9), 0x60003800); in a4xx_hw_init()
234 gpu_write(gpu, REG_A4XX_CP_PROTECT(10), 0x61003980); in a4xx_hw_init()
237 gpu_write(gpu, REG_A4XX_CP_PROTECT(11), 0x6e010000); in a4xx_hw_init()
239 gpu_write(gpu, REG_A4XX_RBBM_INT_0_MASK, A4XX_INT0_MASK); in a4xx_hw_init()
249 gpu_write(gpu, REG_A4XX_CP_ME_RAM_WADDR, 0); in a4xx_hw_init()
251 gpu_write(gpu, REG_A4XX_CP_ME_RAM_DATA, ptr[i]); in a4xx_hw_init()
258 gpu_write(gpu, REG_A4XX_CP_PFP_UCODE_ADDR, 0); in a4xx_hw_init()
260 gpu_write(gpu, REG_A4XX_CP_PFP_UCODE_DATA, ptr[i]); in a4xx_hw_init()
263 gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0); in a4xx_hw_init()
277 gpu_write(gpu, REG_A4XX_RBBM_SW_RESET_CMD, 1); in a4xx_recover()
279 gpu_write(gpu, REG_A4XX_RBBM_SW_RESET_CMD, 0); in a4xx_recover()
320 gpu_write(gpu, REG_A4XX_RBBM_INT_CLEAR_CMD, status); in a4xx_irq()