Lines Matching refs:radeon_crtc
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_overscan_setup() local
47 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
49 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_scaler_setup() local
87 to_radeon_encoder(radeon_crtc->encoder); in atombios_scaler_setup()
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup()
103 args.ucScaler = radeon_crtc->crtc_id; in atombios_scaler_setup()
138 switch (radeon_crtc->rmx_type) { in atombios_scaler_setup()
159 atom_rv515_force_tv_scaler(rdev, radeon_crtc); in atombios_scaler_setup()
165 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_lock_crtc() local
174 args.ucCRTC = radeon_crtc->crtc_id; in atombios_lock_crtc()
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_enable_crtc() local
190 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc()
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_enable_crtc_memreq() local
206 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc_memreq()
224 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_blank_crtc() local
234 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); in atombios_blank_crtc()
235 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); in atombios_blank_crtc()
238 args.ucCRTC = radeon_crtc->crtc_id; in atombios_blank_crtc()
244 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); in atombios_blank_crtc()
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_powergate_crtc() local
258 args.ucDispPipeId = radeon_crtc->crtc_id; in atombios_powergate_crtc()
268 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_dpms() local
272 radeon_crtc->enabled = true; in atombios_crtc_dpms()
277 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); in atombios_crtc_dpms()
285 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); in atombios_crtc_dpms()
286 if (radeon_crtc->enabled) in atombios_crtc_dpms()
291 radeon_crtc->enabled = false; in atombios_crtc_dpms()
302 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_set_crtc_dtd_timing() local
310 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
312 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
313 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
315 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
317 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); in atombios_set_crtc_dtd_timing()
321 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); in atombios_set_crtc_dtd_timing()
324 args.ucH_Border = radeon_crtc->h_border; in atombios_set_crtc_dtd_timing()
325 args.ucV_Border = radeon_crtc->v_border; in atombios_set_crtc_dtd_timing()
341 args.ucCRTC = radeon_crtc->crtc_id; in atombios_set_crtc_dtd_timing()
349 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_set_timing() local
368 args.ucOverscanRight = radeon_crtc->h_border; in atombios_crtc_set_timing()
369 args.ucOverscanLeft = radeon_crtc->h_border; in atombios_crtc_set_timing()
370 args.ucOverscanBottom = radeon_crtc->v_border; in atombios_crtc_set_timing()
371 args.ucOverscanTop = radeon_crtc->v_border; in atombios_crtc_set_timing()
387 args.ucCRTC = radeon_crtc->crtc_id; in atombios_crtc_set_timing()
557 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_adjust_pll() local
560 struct drm_encoder *encoder = radeon_crtc->encoder; in atombios_adjust_pll()
567 int bpc = radeon_crtc->bpc; in atombios_adjust_pll()
571 radeon_crtc->pll_flags = 0; in atombios_adjust_pll()
577 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ in atombios_adjust_pll()
581 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
583 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
586 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; in atombios_adjust_pll()
589 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
592 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
594 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
596 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; in atombios_adjust_pll()
599 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
601 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
624 if (radeon_crtc->ss_enabled) { in atombios_adjust_pll()
625 if (radeon_crtc->ss.refdiv) { in atombios_adjust_pll()
626 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
627 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; in atombios_adjust_pll()
629 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
639 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; in atombios_adjust_pll()
641 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; in atombios_adjust_pll()
644 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; in atombios_adjust_pll()
646 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
691 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
704 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
732 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
733 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
734 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; in atombios_adjust_pll()
737 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
738 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; in atombios_adjust_pll()
739 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; in atombios_adjust_pll()
958 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_prepare_pll() local
962 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
963 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
965 radeon_crtc->bpc = 8; in atombios_crtc_prepare_pll()
966 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
971 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { in atombios_crtc_prepare_pll()
974 radeon_get_connector_for_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
983 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); in atombios_crtc_prepare_pll()
991 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
992 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, in atombios_crtc_prepare_pll()
997 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
999 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1001 if (!radeon_crtc->ss_enabled) in atombios_crtc_prepare_pll()
1002 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1004 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1007 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1009 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1013 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
1018 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1020 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1024 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1026 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1031 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1033 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1039 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1041 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1051 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); in atombios_crtc_prepare_pll()
1058 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_set_pll() local
1062 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_set_pll()
1067 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_set_pll()
1072 (radeon_crtc->bpc > 8)) in atombios_crtc_set_pll()
1073 clock = radeon_crtc->adjusted_clock; in atombios_crtc_set_pll()
1075 switch (radeon_crtc->pll_id) { in atombios_crtc_set_pll()
1090 pll->flags = radeon_crtc->pll_flags; in atombios_crtc_set_pll()
1091 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()
1092 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1096 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1099 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1102 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1105 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1106 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1108 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1111 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); in atombios_crtc_set_pll()
1113 if (radeon_crtc->ss_enabled) { in atombios_crtc_set_pll()
1118 (u32)radeon_crtc->ss.percentage) / in atombios_crtc_set_pll()
1119 (100 * (u32)radeon_crtc->ss.percentage_divider); in atombios_crtc_set_pll()
1120 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; in atombios_crtc_set_pll()
1121 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & in atombios_crtc_set_pll()
1123 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) in atombios_crtc_set_pll()
1124 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1127 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1129 radeon_crtc->ss.step = step_size; in atombios_crtc_set_pll()
1132 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1133 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1141 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in dce4_crtc_do_set_base() local
1354 switch (radeon_crtc->crtc_id) { in dce4_crtc_do_set_base()
1377 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1379 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1381 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1383 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1385 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in dce4_crtc_do_set_base()
1386 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in dce4_crtc_do_set_base()
1393 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1400 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1401 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1402 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1403 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1404 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in dce4_crtc_do_set_base()
1405 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in dce4_crtc_do_set_base()
1408 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in dce4_crtc_do_set_base()
1409 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in dce4_crtc_do_set_base()
1412 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1415 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1419 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1426 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1431 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); in dce4_crtc_do_set_base()
1433 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_crtc_do_set_base()
1436 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); in dce4_crtc_do_set_base()
1458 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in avivo_crtc_do_set_base() local
1578 if (radeon_crtc->crtc_id == 0) in avivo_crtc_do_set_base()
1584 if (radeon_crtc->crtc_id) { in avivo_crtc_do_set_base()
1592 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1595 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()
1596 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in avivo_crtc_do_set_base()
1598 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in avivo_crtc_do_set_base()
1601 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1607 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1608 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1609 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1610 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1611 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in avivo_crtc_do_set_base()
1612 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in avivo_crtc_do_set_base()
1615 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in avivo_crtc_do_set_base()
1616 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in avivo_crtc_do_set_base()
1618 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1622 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1626 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1631 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); in avivo_crtc_do_set_base()
1633 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); in avivo_crtc_do_set_base()
1636 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); in avivo_crtc_do_set_base()
1688 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_legacy_atom_fixup() local
1691 switch (radeon_crtc->crtc_id) { in radeon_legacy_atom_fixup()
1718 struct radeon_crtc *test_radeon_crtc; in radeon_get_pll_use_mask()
1746 struct radeon_crtc *test_radeon_crtc; in radeon_get_shared_dp_ppll()
1777 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_get_shared_nondp_ppll() local
1781 struct radeon_crtc *test_radeon_crtc; in radeon_get_shared_nondp_ppll()
1784 adjusted_clock = radeon_crtc->adjusted_clock; in radeon_get_shared_nondp_ppll()
1800 if (test_radeon_crtc->connector == radeon_crtc->connector) { in radeon_get_shared_nondp_ppll()
1809 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && in radeon_get_shared_nondp_ppll()
1856 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_atom_pick_pll() local
1860 to_radeon_encoder(radeon_crtc->encoder); in radeon_atom_pick_pll()
1865 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1912 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1939 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1962 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
2008 return radeon_crtc->crtc_id; in radeon_atom_pick_pll()
2037 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_mode_set() local
2041 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_set()
2048 if (!radeon_crtc->adjusted_clock) in atombios_crtc_mode_set()
2062 if (radeon_crtc->crtc_id == 0) in atombios_crtc_mode_set()
2071 radeon_crtc->hw_mode = *adjusted_mode; in atombios_crtc_mode_set()
2080 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_mode_fixup() local
2087 radeon_crtc->encoder = encoder; in atombios_crtc_mode_fixup()
2088 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); in atombios_crtc_mode_fixup()
2092 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { in atombios_crtc_mode_fixup()
2093 radeon_crtc->encoder = NULL; in atombios_crtc_mode_fixup()
2094 radeon_crtc->connector = NULL; in atombios_crtc_mode_fixup()
2097 if (radeon_crtc->encoder) { in atombios_crtc_mode_fixup()
2099 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_fixup()
2101 radeon_crtc->output_csc = radeon_encoder->output_csc; in atombios_crtc_mode_fixup()
2108 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); in atombios_crtc_mode_fixup()
2110 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && in atombios_crtc_mode_fixup()
2111 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) in atombios_crtc_mode_fixup()
2138 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_disable() local
2162 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2164 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2172 i != radeon_crtc->crtc_id && in atombios_crtc_disable()
2173 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_disable()
2181 switch (radeon_crtc->pll_id) { in atombios_crtc_disable()
2185 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2194 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2201 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in atombios_crtc_disable()
2202 radeon_crtc->adjusted_clock = 0; in atombios_crtc_disable()
2203 radeon_crtc->encoder = NULL; in atombios_crtc_disable()
2204 radeon_crtc->connector = NULL; in atombios_crtc_disable()
2220 struct radeon_crtc *radeon_crtc) in radeon_atombios_init_crtc() argument
2225 switch (radeon_crtc->crtc_id) { in radeon_atombios_init_crtc()
2228 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2231 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2234 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2237 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2240 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2243 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2247 if (radeon_crtc->crtc_id == 1) in radeon_atombios_init_crtc()
2248 radeon_crtc->crtc_offset = in radeon_atombios_init_crtc()
2251 radeon_crtc->crtc_offset = 0; in radeon_atombios_init_crtc()
2253 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in radeon_atombios_init_crtc()
2254 radeon_crtc->adjusted_clock = 0; in radeon_atombios_init_crtc()
2255 radeon_crtc->encoder = NULL; in radeon_atombios_init_crtc()
2256 radeon_crtc->connector = NULL; in radeon_atombios_init_crtc()
2257 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); in radeon_atombios_init_crtc()