Lines Matching refs:ss
444 struct radeon_atom_ss *ss) in atombios_crtc_program_ss() argument
456 if (ss->percentage == 0) in atombios_crtc_program_ss()
458 if (ss->type & ATOM_EXTERNAL_SS_MASK) in atombios_crtc_program_ss()
479 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
493 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
494 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
497 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
498 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
512 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
513 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
516 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
517 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
518 args.v1.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
519 args.v1.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
520 args.v1.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
524 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || in atombios_crtc_program_ss()
525 (ss->type & ATOM_EXTERNAL_SS_MASK)) { in atombios_crtc_program_ss()
529 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
530 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
531 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
532 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
533 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
540 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
541 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
542 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; in atombios_crtc_program_ss()
543 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; in atombios_crtc_program_ss()
625 if (radeon_crtc->ss.refdiv) { in atombios_adjust_pll()
627 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; in atombios_adjust_pll()
691 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
704 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
828 struct radeon_atom_ss *ss) in atombios_crtc_program_pll() argument
878 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
891 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
920 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
992 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, in atombios_crtc_prepare_pll()
999 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1004 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1009 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1020 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1026 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1033 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1041 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1106 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1111 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); in atombios_crtc_set_pll()
1118 (u32)radeon_crtc->ss.percentage) / in atombios_crtc_set_pll()
1119 (100 * (u32)radeon_crtc->ss.percentage_divider); in atombios_crtc_set_pll()
1120 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; in atombios_crtc_set_pll()
1121 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & in atombios_crtc_set_pll()
1123 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) in atombios_crtc_set_pll()
1124 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1127 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1129 radeon_crtc->ss.step = step_size; in atombios_crtc_set_pll()
1133 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
2018 struct radeon_atom_ss ss; in radeon_atom_disp_eng_pll_init() local
2019 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, in radeon_atom_disp_eng_pll_init()
2023 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); in radeon_atom_disp_eng_pll_init()
2027 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); in radeon_atom_disp_eng_pll_init()
2141 struct radeon_atom_ss ss; in atombios_crtc_disable() local
2186 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); in atombios_crtc_disable()
2195 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); in atombios_crtc_disable()