Lines Matching refs:pi
195 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi() local
197 return pi; in ci_get_pi()
209 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults() local
219 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
225 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
229 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
233 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
243 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
247 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
249 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
250 pi->caps_cac = false; in ci_initialize_powertune_defaults()
251 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
252 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
253 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
254 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
256 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
257 pi->caps_cac = true; in ci_initialize_powertune_defaults()
259 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
261 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
262 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
263 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
274 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_vid_sidd() local
275 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
276 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
277 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
303 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_vddc_vid() local
304 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
307 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
310 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
311 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
318 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_svi_load_line() local
319 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
321 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
322 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
323 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
324 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
331 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_tdc_limit() local
332 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
336 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
337 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
339 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
346 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_dw8() local
347 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
354 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
355 pi->sram_end); in ci_populate_dw8()
359 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
366 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_fuzzy_fan() local
373 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
381 struct ci_power_info *pi = ci_get_pi(rdev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
382 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
383 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
405 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
406 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
413 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_base_leakage_sidd() local
414 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
415 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
422 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
423 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
430 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_parameters_in_dpm_table() local
431 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
432 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
443 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
445 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
478 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_pm_base() local
482 if (pi->caps_power_containment) { in ci_populate_pm_base()
486 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
514 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
515 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
525 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_enable_didt() local
528 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
537 if (pi->caps_db_ramping) { in ci_do_enable_didt()
546 if (pi->caps_td_ramping) { in ci_do_enable_didt()
555 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
615 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_didt() local
618 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
619 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
640 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_power_containment() local
645 pi->power_containment_features = 0; in ci_enable_power_containment()
646 if (pi->caps_power_containment) { in ci_enable_power_containment()
647 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
652 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
655 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
660 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
663 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
673 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
680 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
681 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
684 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
687 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
689 pi->power_containment_features = 0; in ci_enable_power_containment()
698 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_smc_cac() local
702 if (pi->caps_cac) { in ci_enable_smc_cac()
707 pi->cac_enabled = false; in ci_enable_smc_cac()
709 pi->cac_enabled = true; in ci_enable_smc_cac()
711 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
713 pi->cac_enabled = false; in ci_enable_smc_cac()
723 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_thermal_based_sclk_dpm() local
726 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
741 struct ci_power_info *pi = ci_get_pi(rdev); in ci_power_control_set_level() local
749 if (pi->caps_power_containment) { in ci_power_control_set_level()
763 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_powergate_uvd() local
765 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
768 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
775 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_vblank_too_short() local
777 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; in ci_dpm_vblank_too_short()
796 struct ci_power_info *pi = ci_get_pi(rdev); in ci_apply_state_adjust_rules() local
817 pi->battery_state = true; in ci_apply_state_adjust_rules()
819 pi->battery_state = false; in ci_apply_state_adjust_rules()
934 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_static_mode() local
937 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
939 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
941 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
942 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
956 struct ci_power_info *pi = ci_get_pi(rdev); in ci_thermal_setup_fan_table() local
965 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
1018 pi->fan_table_start, in ci_thermal_setup_fan_table()
1021 pi->sram_end); in ci_thermal_setup_fan_table()
1033 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_start_smc_fan_control() local
1036 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1055 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1062 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_stop_smc_fan_control() local
1066 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1103 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_fan_speed_percent() local
1108 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_set_fan_speed_percent()
1148 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_get_mode() local
1151 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_get_mode()
1212 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_default_mode() local
1215 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1217 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); in ci_fan_ctrl_set_default_mode()
1221 tmp |= TMIN(pi->t_min); in ci_fan_ctrl_set_default_mode()
1223 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1281 struct ci_power_info *pi = ci_get_pi(rdev);
1284 pi->soft_regs_start + reg_offset,
1285 value, pi->sram_end);
1292 struct ci_power_info *pi = ci_get_pi(rdev); in ci_write_smc_soft_register() local
1295 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1296 value, pi->sram_end); in ci_write_smc_soft_register()
1301 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_fps_limits() local
1302 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1304 if (pi->caps_fps) { in ci_init_fps_limits()
1317 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_sclk_t() local
1321 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1322 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1325 pi->dpm_table_start + in ci_update_sclk_t()
1328 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1337 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_leakage_voltages() local
1342 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1343 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1351 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1352 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1353 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1363 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1364 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1365 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1368 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1369 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1370 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1379 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_dpm_event_sources() local
1414 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1430 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_auto_throttle_source() local
1433 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1434 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1435 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1438 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1439 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1440 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1453 struct ci_power_info *pi = ci_get_pi(rdev); in ci_unfreeze_sclk_mclk_dpm() local
1456 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1459 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1460 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1466 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1467 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1473 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1479 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_sclk_mclk_dpm() local
1483 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1489 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1507 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1513 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1525 struct ci_power_info *pi = ci_get_pi(rdev); in ci_start_dpm() local
1550 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1561 struct ci_power_info *pi = ci_get_pi(rdev); in ci_freeze_sclk_mclk_dpm() local
1564 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1567 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1568 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1574 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1575 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1586 struct ci_power_info *pi = ci_get_pi(rdev); in ci_stop_dpm() local
1599 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1631 struct ci_power_info *pi = ci_get_pi(rdev);
1643 if (pi->caps_automatic_dc_transition) {
1676 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_sclk() local
1678 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1690 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_mclk() local
1692 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1704 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_pcie() local
1706 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1718 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_power_limit() local
1720 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1794 struct ci_power_info *pi = ci_get_pi(rdev); in ci_process_firmware_header() local
1801 &tmp, pi->sram_end); in ci_process_firmware_header()
1805 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1810 &tmp, pi->sram_end); in ci_process_firmware_header()
1814 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1819 &tmp, pi->sram_end); in ci_process_firmware_header()
1823 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1828 &tmp, pi->sram_end); in ci_process_firmware_header()
1832 pi->fan_table_start = tmp; in ci_process_firmware_header()
1837 &tmp, pi->sram_end); in ci_process_firmware_header()
1841 pi->arb_table_start = tmp; in ci_process_firmware_header()
1848 struct ci_power_info *pi = ci_get_pi(rdev); in ci_read_clock_registers() local
1850 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1852 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1854 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1856 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1858 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1860 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1862 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1863 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1864 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1865 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1866 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1867 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1868 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1869 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
1870 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in ci_read_clock_registers()
1875 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_sclk_t() local
1877 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1941 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ds_master_switch() local
1944 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1952 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1997 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_spread_spectrum() local
2001 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2071 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_firmware() local
2083 ret = ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2112 struct ci_power_info *pi = ci_get_pi(rdev); in ci_construct_voltage_tables() local
2115 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2118 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2121 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2124 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2129 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2131 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2133 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2136 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2139 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2142 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2147 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2149 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2151 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2154 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2157 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2160 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2165 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2167 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2197 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddc_table() local
2200 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2203 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2206 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2208 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2221 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddci_table() local
2223 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2226 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2229 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2231 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2243 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_mvdd_table() local
2246 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2249 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2252 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2254 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2286 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mvdd_value() local
2289 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2292 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2391 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_arb_table_index() local
2395 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2396 &tmp, pi->sram_end); in ci_init_arb_table_index()
2403 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2404 tmp, pi->sram_end); in ci_init_arb_table_index()
2524 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_program_memory_timing_parameters() local
2531 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2532 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2534 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2535 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2544 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2547 pi->sram_end); in ci_do_program_memory_timing_parameters()
2554 struct ci_power_info *pi = ci_get_pi(rdev); in ci_program_memory_timing_parameters() local
2556 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2566 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_initial_state() local
2572 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2580 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2605 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_link_level() local
2606 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2619 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2620 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2770 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_mclk_params() local
2771 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2772 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2773 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2774 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2775 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2776 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2777 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2778 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2779 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2797 if (pi->mem_gddr5) { in ci_calculate_mclk_params()
2803 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2855 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_memory_level() local
2885 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
2895 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
2905 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
2906 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
2907 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
2912 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
2913 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
2916 if (pi->mem_gddr5) { in ci_populate_single_memory_level()
2919 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
2920 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
2923 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2924 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
2934 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
2968 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_acpi_level() local
2971 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
2972 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
2973 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
2974 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
2979 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
2980 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2982 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2984 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
3006 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3007 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3008 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3009 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3028 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3029 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3031 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3034 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3051 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3053 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3055 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3057 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3059 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3060 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3061 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3069 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3083 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ulv() local
3084 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3101 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_ulv_level() local
3108 pi->ulv.supported = false; in ci_populate_ulv_level()
3112 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3126 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3139 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_sclk_params() local
3141 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3142 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3143 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3144 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3163 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3196 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_graphic_level() local
3214 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3230 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3254 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_graphic_levels() local
3255 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3256 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3260 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3268 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3269 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3273 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3275 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3278 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3280 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3281 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3286 pi->sram_end); in ci_populate_all_graphic_levels()
3301 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_memory_levels() local
3302 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3303 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3307 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3317 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3322 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3326 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3327 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3328 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3329 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3332 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3334 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3335 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3338 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3343 pi->sram_end); in ci_populate_all_memory_levels()
3371 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_pcie_tables() local
3373 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3376 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3377 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3378 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3379 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3380 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3381 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3385 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3389 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3390 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3391 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3393 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3394 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3395 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3396 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3397 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3398 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3399 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3400 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3401 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3402 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3403 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3404 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3405 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3406 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3407 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3408 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3409 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3410 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3412 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3419 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_dpm_tables() local
3437 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3440 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3443 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3446 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3449 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3452 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3455 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3458 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3460 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3462 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3464 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3468 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3471 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3473 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3475 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3477 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3482 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3484 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3486 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3488 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3493 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3495 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3497 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3503 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3505 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3507 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3533 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_smc_table() local
3534 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3536 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3543 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3554 if (pi->mem_gddr5) in ci_init_smc_table()
3558 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3605 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3606 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3607 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3609 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3610 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3611 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3613 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3614 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3615 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3632 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3634 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3642 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3644 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3668 pi->dpm_table_start + in ci_init_smc_table()
3672 pi->sram_end); in ci_init_smc_table()
3698 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_pcie_dpm_states() local
3699 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3729 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_dpm_states() local
3741 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3746 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3793 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_dpm_level_enable_mask() local
3798 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3799 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3802 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3808 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3809 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3812 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3818 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3819 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3822 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3834 struct ci_power_info *pi = ci_get_pi(rdev); in ci_find_dpm_states_clocks_in_dpm_table() local
3836 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3838 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3842 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3850 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3854 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3863 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3867 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3873 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3877 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3880 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3883 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3886 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3889 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3895 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3906 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_uvd_dpm() local
3916 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3920 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
3922 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
3929 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
3931 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3932 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
3933 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3936 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3939 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3940 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
3941 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
3944 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3955 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_vce_dpm() local
3965 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3968 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
3970 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
3977 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
3988 struct ci_power_info *pi = ci_get_pi(rdev);
3998 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4001 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4003 if (!pi->caps_samu_dpm)
4010 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4019 struct ci_power_info *pi = ci_get_pi(rdev);
4029 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4032 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4034 if (!pi->caps_acp_dpm)
4041 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4052 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_uvd_dpm() local
4056 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4058 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4060 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4065 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4091 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_vce_dpm() local
4100 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4103 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4125 struct ci_power_info *pi = ci_get_pi(rdev);
4129 pi->smc_state_table.AcpBootLevel = 0;
4133 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4144 struct ci_power_info *pi = ci_get_pi(rdev); in ci_generate_dpm_level_enable_mask() local
4151 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4152 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4153 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4154 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4155 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4156 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4157 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4158 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4159 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4161 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4162 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4182 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_performance_level() local
4187 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4188 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4190 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4206 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4207 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4209 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4225 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4226 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4228 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4245 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4246 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4248 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4260 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4261 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4263 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4275 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4276 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4278 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4291 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4312 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_mc_special_registers() local
4338 if (!pi->mem_gddr5) in ci_set_mc_special_registers()
4345 if (!pi->mem_gddr5) { in ci_set_mc_special_registers()
4599 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_mc_reg_table() local
4601 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4659 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mc_reg_addresses() local
4662 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4663 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4666 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4667 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4695 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_entry_to_smc() local
4698 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4699 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4703 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4706 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4707 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4708 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4714 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_to_smc() local
4717 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4719 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4725 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_initial_mc_reg_table() local
4728 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4730 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4733 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4736 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4737 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4739 pi->sram_end); in ci_populate_initial_mc_reg_table()
4744 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_and_upload_mc_reg_table() local
4746 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4749 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4751 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4754 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4756 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4758 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4759 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4826 struct ci_power_info *pi = ci_get_pi(rdev); in ci_request_link_speed_change_before_state_change() local
4831 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4834 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4836 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4837 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
4844 pi->force_pcie_gen = RADEON_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
4852 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4857 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
4865 struct ci_power_info *pi = ci_get_pi(rdev); in ci_notify_link_speed_change_after_state_change() local
4870 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
4890 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_private_data_variables_based_on_pptable() local
4911 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4912 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4915 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4916 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4933 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddc_leakage() local
4934 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
4947 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddci_leakage() local
4948 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5066 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_memory_type() local
5073 pi->mem_gddr5 = true; in ci_get_memory_type()
5075 pi->mem_gddr5 = false; in ci_get_memory_type()
5083 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_current_ps() local
5085 pi->current_rps = *rps; in ci_update_current_ps()
5086 pi->current_ps = *new_ps; in ci_update_current_ps()
5087 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5094 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_requested_ps() local
5096 pi->requested_rps = *rps; in ci_update_requested_ps()
5097 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5098 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5103 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_pre_set_power_state() local
5109 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5116 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_post_set_power_state() local
5117 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5138 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_enable() local
5144 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5152 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5155 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5157 if (pi->dynamic_ss) in ci_dpm_enable()
5159 if (pi->thermal_protection) in ci_dpm_enable()
5189 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5293 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_disable() local
5303 if (pi->thermal_protection) in ci_dpm_disable()
5324 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_set_power_state() local
5325 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5326 struct radeon_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5330 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5359 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5381 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5449 struct ci_power_info *pi = ci_get_pi(rdev); in ci_parse_pplib_clock_info() local
5461 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5462 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5465 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5469 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5473 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5474 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5475 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5480 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5481 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5482 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5483 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5488 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5489 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5490 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5491 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5492 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5493 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5494 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5495 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5496 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5499 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5500 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5501 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5502 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5503 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5504 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5505 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5506 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5507 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5651 struct ci_power_info *pi; in ci_dpm_init() local
5655 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5656 if (pi == NULL) in ci_dpm_init()
5658 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5662 pi->sys_pcie_mask = 0; in ci_dpm_init()
5664 pi->sys_pcie_mask = mask; in ci_dpm_init()
5665 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_dpm_init()
5667 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5668 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5669 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5670 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5672 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5673 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5674 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5675 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5677 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5701 pi->dll_default_on = false; in ci_dpm_init()
5702 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5704 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5705 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5706 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5707 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5708 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5709 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5710 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5711 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5713 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5715 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5716 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5717 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5718 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5723 pi->mclk_dpm_key_disabled = 1; in ci_dpm_init()
5726 pi->caps_sclk_ds = true; in ci_dpm_init()
5728 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5729 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5730 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5731 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5735 pi->caps_fps = false; in ci_dpm_init()
5737 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5739 pi->caps_uvd_dpm = true; in ci_dpm_init()
5740 pi->caps_vce_dpm = true; in ci_dpm_init()
5772 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5773 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5774 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5776 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5777 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5778 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5781 pi->uvd_enabled = false; in ci_dpm_init()
5783 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5832 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5833 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5834 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5836 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5838 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5842 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5844 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5851 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5853 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5858 pi->vddc_phase_shed_control = true; in ci_dpm_init()
5861 pi->pcie_performance_request = in ci_dpm_init()
5864 pi->pcie_performance_request = false; in ci_dpm_init()
5869 pi->caps_sclk_ss_support = true; in ci_dpm_init()
5870 pi->caps_mclk_ss_support = true; in ci_dpm_init()
5871 pi->dynamic_ss = true; in ci_dpm_init()
5873 pi->caps_sclk_ss_support = false; in ci_dpm_init()
5874 pi->caps_mclk_ss_support = false; in ci_dpm_init()
5875 pi->dynamic_ss = true; in ci_dpm_init()
5879 pi->thermal_protection = true; in ci_dpm_init()
5881 pi->thermal_protection = false; in ci_dpm_init()
5883 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
5885 pi->uvd_power_gated = false; in ci_dpm_init()
5893 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
5901 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5902 struct radeon_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
5906 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5946 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_sclk() local
5947 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
5957 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_mclk() local
5958 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()