Lines Matching refs:table
1302 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits() local
1308 table->FpsHighT = cpu_to_be16(tmp); in ci_init_fps_limits()
1311 table->FpsLowT = cpu_to_be16(tmp); in ci_init_fps_limits()
2195 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddc_table() argument
2200 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2201 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
2204 &table->VddcLevel[count]); in ci_populate_smc_vddc_table()
2207 table->VddcLevel[count].Smio |= in ci_populate_smc_vddc_table()
2210 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
2212 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); in ci_populate_smc_vddc_table()
2218 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddci_table() argument
2223 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2224 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vddci_table()
2227 &table->VddciLevel[count]); in ci_populate_smc_vddci_table()
2230 table->VddciLevel[count].Smio |= in ci_populate_smc_vddci_table()
2233 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vddci_table()
2235 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); in ci_populate_smc_vddci_table()
2241 SMU7_Discrete_DpmTable *table) in ci_populate_smc_mvdd_table() argument
2246 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2247 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
2250 &table->MvddLevel[count]); in ci_populate_smc_mvdd_table()
2253 table->MvddLevel[count].Smio |= in ci_populate_smc_mvdd_table()
2256 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
2258 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); in ci_populate_smc_mvdd_table()
2264 SMU7_Discrete_DpmTable *table) in ci_populate_smc_voltage_tables() argument
2268 ret = ci_populate_smc_vddc_table(rdev, table); in ci_populate_smc_voltage_tables()
2272 ret = ci_populate_smc_vddci_table(rdev, table); in ci_populate_smc_voltage_tables()
2276 ret = ci_populate_smc_mvdd_table(rdev, table); in ci_populate_smc_voltage_tables()
2603 SMU7_Discrete_DpmTable *table) in ci_populate_smc_link_level() argument
2610 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
2612 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
2614 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
2615 table->LinkLevel[i].DownT = cpu_to_be32(5); in ci_populate_smc_link_level()
2616 table->LinkLevel[i].UpT = cpu_to_be32(30); in ci_populate_smc_link_level()
2625 SMU7_Discrete_DpmTable *table) in ci_populate_smc_uvd_level() argument
2631 table->UvdLevelCount = in ci_populate_smc_uvd_level()
2634 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
2635 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
2637 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
2639 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
2641 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
2645 table->UvdLevel[count].VclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2649 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2653 table->UvdLevel[count].DclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2657 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2659 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
2660 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
2661 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); in ci_populate_smc_uvd_level()
2668 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vce_level() argument
2674 table->VceLevelCount = in ci_populate_smc_vce_level()
2677 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
2678 table->VceLevel[count].Frequency = in ci_populate_smc_vce_level()
2680 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
2682 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
2686 table->VceLevel[count].Frequency, false, ÷rs); in ci_populate_smc_vce_level()
2690 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2692 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
2693 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
2701 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acp_level() argument
2707 table->AcpLevelCount = (u8) in ci_populate_smc_acp_level()
2710 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
2711 table->AcpLevel[count].Frequency = in ci_populate_smc_acp_level()
2713 table->AcpLevel[count].MinVoltage = in ci_populate_smc_acp_level()
2715 table->AcpLevel[count].MinPhases = 1; in ci_populate_smc_acp_level()
2719 table->AcpLevel[count].Frequency, false, ÷rs); in ci_populate_smc_acp_level()
2723 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2725 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); in ci_populate_smc_acp_level()
2726 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); in ci_populate_smc_acp_level()
2733 SMU7_Discrete_DpmTable *table) in ci_populate_smc_samu_level() argument
2739 table->SamuLevelCount = in ci_populate_smc_samu_level()
2742 for (count = 0; count < table->SamuLevelCount; count++) { in ci_populate_smc_samu_level()
2743 table->SamuLevel[count].Frequency = in ci_populate_smc_samu_level()
2745 table->SamuLevel[count].MinVoltage = in ci_populate_smc_samu_level()
2747 table->SamuLevel[count].MinPhases = 1; in ci_populate_smc_samu_level()
2751 table->SamuLevel[count].Frequency, false, ÷rs); in ci_populate_smc_samu_level()
2755 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
2757 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); in ci_populate_smc_samu_level()
2758 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); in ci_populate_smc_samu_level()
2966 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acpi_level() argument
2977 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; in ci_populate_smc_acpi_level()
2980 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2982 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2984 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
2986 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
2990 table->ACPILevel.SclkFrequency, false, ÷rs); in ci_populate_smc_acpi_level()
2994 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
2995 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_smc_acpi_level()
2996 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
3004 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; in ci_populate_smc_acpi_level()
3005 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; in ci_populate_smc_acpi_level()
3006 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3007 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3008 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3009 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3010 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
3011 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
3013 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); in ci_populate_smc_acpi_level()
3014 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); in ci_populate_smc_acpi_level()
3015 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); in ci_populate_smc_acpi_level()
3016 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); in ci_populate_smc_acpi_level()
3017 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); in ci_populate_smc_acpi_level()
3018 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); in ci_populate_smc_acpi_level()
3019 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); in ci_populate_smc_acpi_level()
3020 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); in ci_populate_smc_acpi_level()
3021 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); in ci_populate_smc_acpi_level()
3022 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); in ci_populate_smc_acpi_level()
3023 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); in ci_populate_smc_acpi_level()
3025 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; in ci_populate_smc_acpi_level()
3026 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
3030 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3033 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3038 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
3040 table->MemoryACPILevel.MinMvdd = in ci_populate_smc_acpi_level()
3048 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); in ci_populate_smc_acpi_level()
3049 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); in ci_populate_smc_acpi_level()
3050 table->MemoryACPILevel.MpllAdFuncCntl = in ci_populate_smc_acpi_level()
3052 table->MemoryACPILevel.MpllDqFuncCntl = in ci_populate_smc_acpi_level()
3054 table->MemoryACPILevel.MpllFuncCntl = in ci_populate_smc_acpi_level()
3056 table->MemoryACPILevel.MpllFuncCntl_1 = in ci_populate_smc_acpi_level()
3058 table->MemoryACPILevel.MpllFuncCntl_2 = in ci_populate_smc_acpi_level()
3060 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3061 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3063 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
3064 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
3065 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
3066 table->MemoryACPILevel.DownH = 100; in ci_populate_smc_acpi_level()
3067 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
3068 table->MemoryACPILevel.ActivityLevel = in ci_populate_smc_acpi_level()
3071 table->MemoryACPILevel.StutterEnable = false; in ci_populate_smc_acpi_level()
3072 table->MemoryACPILevel.StrobeEnable = false; in ci_populate_smc_acpi_level()
3073 table->MemoryACPILevel.EdcReadEnable = false; in ci_populate_smc_acpi_level()
3074 table->MemoryACPILevel.EdcWriteEnable = false; in ci_populate_smc_acpi_level()
3075 table->MemoryACPILevel.RttEnable = false; in ci_populate_smc_acpi_level()
3515 static int ci_find_boot_level(struct ci_single_dpm_table *table, in ci_find_boot_level() argument
3521 for(i = 0; i < table->count; i++) { in ci_find_boot_level()
3522 if (value == table->dpm_levels[i].value) { in ci_find_boot_level()
3536 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table() local
3544 ci_populate_smc_voltage_tables(rdev, table); in ci_init_smc_table()
3549 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in ci_init_smc_table()
3552 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in ci_init_smc_table()
3555 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in ci_init_smc_table()
3572 ci_populate_smc_link_level(rdev, table); in ci_init_smc_table()
3574 ret = ci_populate_smc_acpi_level(rdev, table); in ci_init_smc_table()
3578 ret = ci_populate_smc_vce_level(rdev, table); in ci_init_smc_table()
3582 ret = ci_populate_smc_acp_level(rdev, table); in ci_init_smc_table()
3586 ret = ci_populate_smc_samu_level(rdev, table); in ci_init_smc_table()
3594 ret = ci_populate_smc_uvd_level(rdev, table); in ci_init_smc_table()
3598 table->UvdBootLevel = 0; in ci_init_smc_table()
3599 table->VceBootLevel = 0; in ci_init_smc_table()
3600 table->AcpBootLevel = 0; in ci_init_smc_table()
3601 table->SamuBootLevel = 0; in ci_init_smc_table()
3602 table->GraphicsBootLevel = 0; in ci_init_smc_table()
3603 table->MemoryBootLevel = 0; in ci_init_smc_table()
3613 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3614 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3615 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3623 table->UVDInterval = 1; in ci_init_smc_table()
3624 table->VCEInterval = 1; in ci_init_smc_table()
3625 table->ACPInterval = 1; in ci_init_smc_table()
3626 table->SAMUInterval = 1; in ci_init_smc_table()
3627 table->GraphicsVoltageChangeEnable = 1; in ci_init_smc_table()
3628 table->GraphicsThermThrottleEnable = 1; in ci_init_smc_table()
3629 table->GraphicsInterval = 1; in ci_init_smc_table()
3630 table->VoltageInterval = 1; in ci_init_smc_table()
3631 table->ThermalInterval = 1; in ci_init_smc_table()
3632 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3634 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3636 table->MemoryVoltageChangeEnable = 1; in ci_init_smc_table()
3637 table->MemoryInterval = 1; in ci_init_smc_table()
3638 table->VoltageResponseTime = 0; in ci_init_smc_table()
3639 table->VddcVddciDelta = 4000; in ci_init_smc_table()
3640 table->PhaseResponseTime = 0; in ci_init_smc_table()
3641 table->MemoryThermThrottleEnable = 1; in ci_init_smc_table()
3642 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3643 table->PCIeGenInterval = 1; in ci_init_smc_table()
3645 table->SVI2Enable = 1; in ci_init_smc_table()
3647 table->SVI2Enable = 0; in ci_init_smc_table()
3649 table->ThermGpio = 17; in ci_init_smc_table()
3650 table->SclkStepSize = 0x4000; in ci_init_smc_table()
3652 table->SystemFlags = cpu_to_be32(table->SystemFlags); in ci_init_smc_table()
3653 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); in ci_init_smc_table()
3654 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); in ci_init_smc_table()
3655 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); in ci_init_smc_table()
3656 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); in ci_init_smc_table()
3657 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); in ci_init_smc_table()
3658 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); in ci_init_smc_table()
3659 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); in ci_init_smc_table()
3660 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); in ci_init_smc_table()
3661 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); in ci_init_smc_table()
3662 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); in ci_init_smc_table()
3663 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); in ci_init_smc_table()
3664 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); in ci_init_smc_table()
3665 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); in ci_init_smc_table()
3670 (u8 *)&table->SystemFlags, in ci_init_smc_table()
4076 struct radeon_vce_clock_voltage_dependency_table *table = in ci_get_vce_boot_level() local
4079 for (i = 0; i < table->count; i++) { in ci_get_vce_boot_level()
4080 if (table->entries[i].evclk >= min_evclk) in ci_get_vce_boot_level()
4084 return table->count - 1; in ci_get_vce_boot_level()
4310 struct ci_mc_reg_table *table) in ci_set_mc_special_registers() argument
4316 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
4319 switch(table->mc_reg_address[i].s1 << 2) { in ci_set_mc_special_registers()
4322 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ci_set_mc_special_registers()
4323 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ci_set_mc_special_registers()
4324 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4325 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4326 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
4333 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ci_set_mc_special_registers()
4334 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ci_set_mc_special_registers()
4335 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4336 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4337 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4339 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
4346 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
4347 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
4348 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4349 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4350 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
4359 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ci_set_mc_special_registers()
4360 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ci_set_mc_special_registers()
4361 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4362 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4363 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4375 table->last = j; in ci_set_mc_special_registers()
4453 static void ci_set_valid_flag(struct ci_mc_reg_table *table) in ci_set_valid_flag() argument
4457 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
4458 for (j = 1; j < table->num_entries; j++) { in ci_set_valid_flag()
4459 if (table->mc_reg_table_entry[j-1].mc_data[i] != in ci_set_valid_flag()
4460 table->mc_reg_table_entry[j].mc_data[i]) { in ci_set_valid_flag()
4461 table->valid_flag |= 1 << i; in ci_set_valid_flag()
4468 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) in ci_set_s0_mc_reg_index() argument
4473 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
4474 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()
4475 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in ci_set_s0_mc_reg_index()
4476 address : table->mc_reg_address[i].s1; in ci_set_s0_mc_reg_index()
4480 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, in ci_copy_vbios_mc_reg_table() argument
4485 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_copy_vbios_mc_reg_table()
4487 if (table->num_entries > MAX_AC_TIMING_ENTRIES) in ci_copy_vbios_mc_reg_table()
4490 for (i = 0; i < table->last; i++) in ci_copy_vbios_mc_reg_table()
4491 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ci_copy_vbios_mc_reg_table()
4493 ci_table->last = table->last; in ci_copy_vbios_mc_reg_table()
4495 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_mc_reg_table()
4497 table->mc_reg_table_entry[i].mclk_max; in ci_copy_vbios_mc_reg_table()
4498 for (j = 0; j < table->last; j++) in ci_copy_vbios_mc_reg_table()
4500 table->mc_reg_table_entry[i].mc_data[j]; in ci_copy_vbios_mc_reg_table()
4502 ci_table->num_entries = table->num_entries; in ci_copy_vbios_mc_reg_table()
4508 struct ci_mc_reg_table *table) in ci_register_patching_mc_seq() argument
4520 for (i = 0; i < table->last; i++) { in ci_register_patching_mc_seq()
4521 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_register_patching_mc_seq()
4523 switch(table->mc_reg_address[i].s1 >> 2) { in ci_register_patching_mc_seq()
4525 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4526 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4527 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4528 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4529 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | in ci_register_patching_mc_seq()
4534 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4535 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4536 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4537 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4538 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4543 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4544 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4545 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4546 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4547 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4552 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4553 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4554 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4555 table->mc_reg_table_entry[k].mc_data[i] = 0; in ci_register_patching_mc_seq()
4559 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4560 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4561 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4562 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4564 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4565 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4566 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4571 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4572 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4573 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4574 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4576 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4577 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4578 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4600 struct atom_mc_reg_table *table; in ci_initialize_mc_reg_table() local
4605 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); in ci_initialize_mc_reg_table()
4606 if (!table) in ci_initialize_mc_reg_table()
4630 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); in ci_initialize_mc_reg_table()
4634 ret = ci_copy_vbios_mc_reg_table(table, ci_table); in ci_initialize_mc_reg_table()
4651 kfree(table); in ci_initialize_mc_reg_table()
4960 struct radeon_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage() argument
4964 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4965 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4966 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4971 struct radeon_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage() argument
4975 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4976 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4977 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4982 struct radeon_vce_clock_voltage_dependency_table *table) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage() argument
4986 if (table) { in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4987 for (i = 0; i < table->count; i++) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4988 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4993 struct radeon_uvd_clock_voltage_dependency_table *table) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage() argument
4997 if (table) { in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4998 for (i = 0; i < table->count; i++) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4999 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
5004 struct radeon_phase_shedding_limits_table *table) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage() argument
5008 if (table) { in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5009 for (i = 0; i < table->count; i++) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5010 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5015 struct radeon_clock_and_voltage_limits *table) in ci_patch_clock_voltage_limits_with_vddc_leakage() argument
5017 if (table) { in ci_patch_clock_voltage_limits_with_vddc_leakage()
5018 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5019 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5024 struct radeon_cac_leakage_table *table) in ci_patch_cac_leakage_table_with_vddc_leakage() argument
5028 if (table) { in ci_patch_cac_leakage_table_with_vddc_leakage()
5029 for (i = 0; i < table->count; i++) in ci_patch_cac_leakage_table_with_vddc_leakage()
5030 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); in ci_patch_cac_leakage_table_with_vddc_leakage()