2753 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2818 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2819 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2822 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2824 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2843 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2844 					src_offset <<= 8;  in evergreen_dma_cs_parse()
2853 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
2854 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2862 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2864 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2877 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2878 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2881 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2883 							src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2923 				src_offset = radeon_get_ib_value(p, idx+3);  in evergreen_dma_cs_parse()
2924 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2925 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2927 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2963 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
2964 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2965 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2967 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3025 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3026 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3027 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3029 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3054 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3055 					src_offset <<= 8;  in evergreen_dma_cs_parse()
3064 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3065 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3073 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3075 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3112 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3113 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3114 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3116 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()