Lines Matching refs:pi
251 struct kv_power_info *pi = rdev->pm.dpm.priv; in kv_get_pi() local
253 return pi; in kv_get_pi()
333 struct kv_power_info *pi = kv_get_pi(rdev); in kv_do_enable_didt() local
336 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
345 if (pi->caps_db_ramping) { in kv_do_enable_didt()
354 if (pi->caps_td_ramping) { in kv_do_enable_didt()
363 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
375 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_didt() local
378 if (pi->caps_sq_ramping || in kv_enable_didt()
379 pi->caps_db_ramping || in kv_enable_didt()
380 pi->caps_td_ramping || in kv_enable_didt()
381 pi->caps_tcp_ramping) { in kv_enable_didt()
403 struct kv_power_info *pi = kv_get_pi(rdev);
405 if (pi->caps_cac) {
435 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_smc_cac() local
438 if (pi->caps_cac) { in kv_enable_smc_cac()
442 pi->cac_enabled = false; in kv_enable_smc_cac()
444 pi->cac_enabled = true; in kv_enable_smc_cac()
445 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
447 pi->cac_enabled = false; in kv_enable_smc_cac()
456 struct kv_power_info *pi = kv_get_pi(rdev); in kv_process_firmware_header() local
462 &tmp, pi->sram_end); in kv_process_firmware_header()
465 pi->dpm_table_start = tmp; in kv_process_firmware_header()
469 &tmp, pi->sram_end); in kv_process_firmware_header()
472 pi->soft_regs_start = tmp; in kv_process_firmware_header()
479 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_dpm_voltage_scaling() local
482 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
485 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
487 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
488 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
495 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_interval() local
498 pi->graphics_interval = 1; in kv_set_dpm_interval()
501 pi->dpm_table_start + in kv_set_dpm_interval()
503 &pi->graphics_interval, in kv_set_dpm_interval()
504 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
511 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_boot_state() local
515 pi->dpm_table_start + in kv_set_dpm_boot_state()
517 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
518 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
536 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_divider_value() local
545 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
546 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
606 struct kv_power_info *pi = kv_get_pi(rdev); in kv_convert_2bit_index_to_voltage() local
608 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
617 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_vid() local
619 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
620 pi->graphics_level[index].MinVddNb = in kv_set_vid()
628 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_at() local
630 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
638 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enable() local
640 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
698 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_sclk_t() local
702 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
703 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
706 pi->dpm_table_start + in kv_update_sclk_t()
709 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
716 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_bootup_state() local
722 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
723 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
727 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
731 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
736 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
737 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
741 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
749 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_auto_thermal_throttling() local
752 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
755 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
757 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
758 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
765 struct kv_power_info *pi = kv_get_pi(rdev); in kv_upload_dpm_settings() local
769 pi->dpm_table_start + in kv_upload_dpm_settings()
771 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
773 pi->sram_end); in kv_upload_dpm_settings()
779 pi->dpm_table_start + in kv_upload_dpm_settings()
781 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
782 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
794 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_clk_bypass() local
797 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
819 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_uvd_table() local
829 pi->uvd_level_count = 0; in kv_populate_uvd_table()
831 if (pi->high_voltage_t && in kv_populate_uvd_table()
832 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
835 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
836 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
837 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
839 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
841 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
848 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
854 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
856 pi->uvd_level_count++; in kv_populate_uvd_table()
860 pi->dpm_table_start + in kv_populate_uvd_table()
862 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
863 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
867 pi->uvd_interval = 1; in kv_populate_uvd_table()
870 pi->dpm_table_start + in kv_populate_uvd_table()
872 &pi->uvd_interval, in kv_populate_uvd_table()
873 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
878 pi->dpm_table_start + in kv_populate_uvd_table()
880 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
882 pi->sram_end); in kv_populate_uvd_table()
890 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_vce_table() local
900 pi->vce_level_count = 0; in kv_populate_vce_table()
902 if (pi->high_voltage_t && in kv_populate_vce_table()
903 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
906 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
907 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
909 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
916 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
918 pi->vce_level_count++; in kv_populate_vce_table()
922 pi->dpm_table_start + in kv_populate_vce_table()
924 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
926 pi->sram_end); in kv_populate_vce_table()
930 pi->vce_interval = 1; in kv_populate_vce_table()
933 pi->dpm_table_start + in kv_populate_vce_table()
935 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
937 pi->sram_end); in kv_populate_vce_table()
942 pi->dpm_table_start + in kv_populate_vce_table()
944 (u8 *)&pi->vce_level, in kv_populate_vce_table()
946 pi->sram_end); in kv_populate_vce_table()
953 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_samu_table() local
963 pi->samu_level_count = 0; in kv_populate_samu_table()
965 if (pi->high_voltage_t && in kv_populate_samu_table()
966 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
969 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
970 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
972 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
979 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
981 pi->samu_level_count++; in kv_populate_samu_table()
985 pi->dpm_table_start + in kv_populate_samu_table()
987 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
989 pi->sram_end); in kv_populate_samu_table()
993 pi->samu_interval = 1; in kv_populate_samu_table()
996 pi->dpm_table_start + in kv_populate_samu_table()
998 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
1000 pi->sram_end); in kv_populate_samu_table()
1005 pi->dpm_table_start + in kv_populate_samu_table()
1007 (u8 *)&pi->samu_level, in kv_populate_samu_table()
1009 pi->sram_end); in kv_populate_samu_table()
1019 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_acp_table() local
1029 pi->acp_level_count = 0; in kv_populate_acp_table()
1031 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
1032 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
1038 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1040 pi->acp_level_count++; in kv_populate_acp_table()
1044 pi->dpm_table_start + in kv_populate_acp_table()
1046 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
1048 pi->sram_end); in kv_populate_acp_table()
1052 pi->acp_interval = 1; in kv_populate_acp_table()
1055 pi->dpm_table_start + in kv_populate_acp_table()
1057 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
1059 pi->sram_end); in kv_populate_acp_table()
1064 pi->dpm_table_start + in kv_populate_acp_table()
1066 (u8 *)&pi->acp_level, in kv_populate_acp_table()
1068 pi->sram_end); in kv_populate_acp_table()
1077 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dfs_bypass_settings() local
1083 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1084 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1086 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1088 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1090 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1092 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1094 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1096 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1098 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1103 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
1104 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1105 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1107 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1109 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1111 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1113 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1115 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1117 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1119 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1133 struct kv_power_info *pi = kv_get_pi(rdev); in kv_reset_acp_boot_level() local
1135 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
1142 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_current_ps() local
1144 pi->current_rps = *rps; in kv_update_current_ps()
1145 pi->current_ps = *new_ps; in kv_update_current_ps()
1146 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
1153 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_requested_ps() local
1155 pi->requested_rps = *rps; in kv_update_requested_ps()
1156 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1157 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1162 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable_bapm() local
1165 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1187 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable() local
1233 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1336 struct kv_power_info *pi = kv_get_pi(rdev);
1338 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1339 (u8 *)&value, sizeof(u16), pi->sram_end);
1345 struct kv_power_info *pi = kv_get_pi(rdev);
1347 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1348 value, pi->sram_end);
1354 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_sclk_t() local
1356 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1361 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_fps_limits() local
1364 if (pi->caps_fps) { in kv_init_fps_limits()
1368 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1370 pi->dpm_table_start + in kv_init_fps_limits()
1372 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1373 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1376 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1379 pi->dpm_table_start + in kv_init_fps_limits()
1381 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1382 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1390 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_powergate_state() local
1392 pi->uvd_power_gated = false; in kv_init_powergate_state()
1393 pi->vce_power_gated = false; in kv_init_powergate_state()
1394 pi->samu_power_gated = false; in kv_init_powergate_state()
1395 pi->acp_power_gated = false; in kv_init_powergate_state()
1425 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_uvd_dpm() local
1433 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1435 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1437 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1438 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1444 pi->dpm_table_start + in kv_update_uvd_dpm()
1446 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1447 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1477 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_vce_dpm() local
1486 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1487 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1489 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); in kv_update_vce_dpm()
1492 pi->dpm_table_start + in kv_update_vce_dpm()
1494 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1496 pi->sram_end); in kv_update_vce_dpm()
1500 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1503 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1518 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_samu_dpm() local
1524 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1525 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1527 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1530 pi->dpm_table_start + in kv_update_samu_dpm()
1532 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1534 pi->sram_end); in kv_update_samu_dpm()
1538 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1541 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1566 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_boot_level() local
1569 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1571 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1572 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1575 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1582 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_dpm() local
1588 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1589 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1591 pi->acp_boot_level = kv_get_acp_boot_level(rdev); in kv_update_acp_dpm()
1594 pi->dpm_table_start + in kv_update_acp_dpm()
1596 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1598 pi->sram_end); in kv_update_acp_dpm()
1602 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1605 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1613 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_uvd() local
1615 if (pi->uvd_power_gated == gate) in kv_dpm_powergate_uvd()
1618 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1621 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1626 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1629 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1641 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_vce() local
1643 if (pi->vce_power_gated == gate) in kv_dpm_powergate_vce()
1646 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1649 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1654 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1664 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_samu() local
1666 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1669 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1673 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1676 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1684 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_acp() local
1686 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1692 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1696 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1699 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1709 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_valid_clock_range() local
1715 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1717 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1718 pi->lowest_valid = i; in kv_set_valid_clock_range()
1723 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1727 pi->highest_valid = i; in kv_set_valid_clock_range()
1729 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1730 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1731 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1732 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1734 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1738 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1740 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1742 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1743 pi->lowest_valid = i; in kv_set_valid_clock_range()
1748 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1753 pi->highest_valid = i; in kv_set_valid_clock_range()
1755 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1757 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1758 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1760 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1762 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1771 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_dfs_bypass_settings() local
1775 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1777 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1779 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1781 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1784 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1793 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_nb_dpm() local
1797 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1800 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1803 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1806 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1839 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_pre_set_power_state() local
1846 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1847 &pi->current_rps); in kv_dpm_pre_set_power_state()
1854 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_set_power_state() local
1855 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1856 struct radeon_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1859 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1868 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1897 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1928 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_post_set_power_state() local
1929 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
1944 struct kv_power_info *pi = kv_get_pi(rdev);
1959 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1969 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_max_power_limits_table() local
1971 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
1972 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
1974 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
1977 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
1980 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
2027 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_boot_state() local
2029 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
2030 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
2031 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
2032 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
2033 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
2034 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
2035 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
2036 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
2082 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_sleep_divider_id_from_clock() local
2091 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
2105 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_high_voltage_limit() local
2112 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2114 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2121 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
2124 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2126 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2142 struct kv_power_info *pi = kv_get_pi(rdev); in kv_apply_state_adjust_rules() local
2164 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2194 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2195 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2203 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2206 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2207 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2215 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2221 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2226 pi->battery_state = true; in kv_apply_state_adjust_rules()
2228 pi->battery_state = false; in kv_apply_state_adjust_rules()
2241 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2242 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2243 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2244 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2256 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enabled_for_throttle() local
2258 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2263 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_ds_divider() local
2267 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2270 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2271 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2273 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2281 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_nbps_level_settings() local
2288 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2292 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2293 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2294 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2295 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2298 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2301 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2302 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2305 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2306 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2308 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2309 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2311 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2312 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2313 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2314 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2317 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2318 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2319 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2320 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2323 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2324 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2325 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2326 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2327 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2335 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dpm_settings() local
2338 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2341 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2342 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2349 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_graphics_levels() local
2357 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2359 if (pi->high_voltage_t && in kv_init_graphics_levels()
2360 (pi->high_voltage_t < in kv_init_graphics_levels()
2366 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2369 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2371 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2375 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2377 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2379 if (pi->high_voltage_t && in kv_init_graphics_levels()
2380 pi->high_voltage_t < in kv_init_graphics_levels()
2386 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2388 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2398 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_new_levels() local
2402 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2418 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_enabled_levels() local
2421 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2433 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_nbps_index_settings() local
2439 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2490 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_sys_info_table() local
2507 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2508 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2509 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2512 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2514 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2516 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2518 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2519 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2524 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2526 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2529 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2531 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2536 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2539 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2543 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2576 struct kv_power_info *pi = kv_get_pi(rdev); in kv_patch_boot_state() local
2579 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2613 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_pplib_clock_info() local
2625 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2722 struct kv_power_info *pi; in kv_dpm_init() local
2725 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2726 if (pi == NULL) in kv_dpm_init()
2728 rdev->pm.dpm.priv = pi; in kv_dpm_init()
2739 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2741 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2745 pi->enable_nb_dpm = false; in kv_dpm_init()
2747 pi->enable_nb_dpm = true; in kv_dpm_init()
2749 pi->caps_power_containment = true; in kv_dpm_init()
2750 pi->caps_cac = true; in kv_dpm_init()
2751 pi->enable_didt = false; in kv_dpm_init()
2752 if (pi->enable_didt) { in kv_dpm_init()
2753 pi->caps_sq_ramping = true; in kv_dpm_init()
2754 pi->caps_db_ramping = true; in kv_dpm_init()
2755 pi->caps_td_ramping = true; in kv_dpm_init()
2756 pi->caps_tcp_ramping = true; in kv_dpm_init()
2759 pi->caps_sclk_ds = true; in kv_dpm_init()
2760 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2761 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2765 pi->bapm_enable = true; in kv_dpm_init()
2767 pi->bapm_enable = false; in kv_dpm_init()
2769 pi->bapm_enable = false; in kv_dpm_init()
2771 pi->bapm_enable = true; in kv_dpm_init()
2773 pi->voltage_drop_t = 0; in kv_dpm_init()
2774 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2775 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2776 pi->caps_uvd_pg = true; in kv_dpm_init()
2777 pi->caps_uvd_dpm = true; in kv_dpm_init()
2778 pi->caps_vce_pg = false; /* XXX true */ in kv_dpm_init()
2779 pi->caps_samu_pg = false; in kv_dpm_init()
2780 pi->caps_acp_pg = false; in kv_dpm_init()
2781 pi->caps_stable_p_state = false; in kv_dpm_init()
2794 pi->enable_dpm = true; in kv_dpm_init()
2802 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_debugfs_print_current_performance_level() local
2812 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2816 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2817 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2825 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_sclk() local
2834 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_get_current_sclk()
2841 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_mclk() local
2843 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_current_mclk()
2883 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_sclk() local
2884 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2894 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_mclk() local
2896 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()