90 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);  in rv370_pcie_gart_tlb_flush()
92 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_tlb_flush()
162 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_enable()
163 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);  in rv370_pcie_gart_enable()
165 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);  in rv370_pcie_gart_enable()
166 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);  in rv370_pcie_gart_enable()
167 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);  in rv370_pcie_gart_enable()
169 	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);  in rv370_pcie_gart_enable()
171 	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);  in rv370_pcie_gart_enable()
172 	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);  in rv370_pcie_gart_enable()
174 	WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);  in rv370_pcie_gart_enable()
178 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_enable()
191 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);  in rv370_pcie_gart_disable()
192 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);  in rv370_pcie_gart_disable()
193 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);  in rv370_pcie_gart_disable()
194 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);  in rv370_pcie_gart_disable()
197 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);  in rv370_pcie_gart_disable()
547 	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in rv370_set_pcie_lanes()
548 	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |  in rv370_set_pcie_lanes()