Lines Matching refs:r600
1992 rdev->config.r600.tiling_group_size = 256; in r600_gpu_init()
1995 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1996 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()
1997 rdev->config.r600.max_simds = 4; in r600_gpu_init()
1998 rdev->config.r600.max_backends = 4; in r600_gpu_init()
1999 rdev->config.r600.max_gprs = 256; in r600_gpu_init()
2000 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2001 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2002 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2003 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2004 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2005 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2006 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2007 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2011 rdev->config.r600.max_pipes = 2; in r600_gpu_init()
2012 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()
2013 rdev->config.r600.max_simds = 3; in r600_gpu_init()
2014 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2015 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2016 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2017 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2018 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2019 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2020 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2021 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2022 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2023 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2029 rdev->config.r600.max_pipes = 1; in r600_gpu_init()
2030 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()
2031 rdev->config.r600.max_simds = 2; in r600_gpu_init()
2032 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2033 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2034 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2035 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2036 rdev->config.r600.max_hw_contexts = 4; in r600_gpu_init()
2037 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2038 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2039 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2040 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2041 rdev->config.r600.sq_num_cf_insts = 1; in r600_gpu_init()
2044 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
2045 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()
2046 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2047 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2048 rdev->config.r600.max_gprs = 192; in r600_gpu_init()
2049 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2050 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2051 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2052 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2053 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2054 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2055 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2056 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2076 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()
2092 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
2093 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); in r600_gpu_init()
2108 tmp = rdev->config.r600.max_simds - in r600_gpu_init()
2110 rdev->config.r600.active_simds = tmp; in r600_gpu_init()
2114 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2118 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2122 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
2125 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
2127 rdev->config.r600.tile_config = tiling_config; in r600_gpu_init()
2301 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
2701 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
3871 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3872 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3873 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3875 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3876 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3878 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3879 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3882 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3883 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3884 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; in r600_irq_ack()
3885 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3886 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3888 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3889 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3891 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3893 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3895 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3897 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3899 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3901 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3903 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3914 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
3925 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_ack()
3936 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_ack()
3942 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_ack()
3947 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_ack()
3952 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3957 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3963 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3968 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4089 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4099 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
4104 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) in r600_irq_process()
4107 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; in r600_irq_process()
4119 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) in r600_irq_process()
4129 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; in r600_irq_process()
4134 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) in r600_irq_process()
4137 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; in r600_irq_process()
4159 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) in r600_irq_process()
4162 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; in r600_irq_process()
4167 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) in r600_irq_process()
4170 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; in r600_irq_process()
4175 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) in r600_irq_process()
4178 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; in r600_irq_process()
4183 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) in r600_irq_process()
4186 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; in r600_irq_process()
4191 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) in r600_irq_process()
4194 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; in r600_irq_process()
4199 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) in r600_irq_process()
4202 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; in r600_irq_process()
4215 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4218 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4224 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4227 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()