748 	u32 gb_tiling_config = 0;  in r600_gfx_init()  local
841 		gb_tiling_config |= R600_PIPE_TILING(0);  in r600_gfx_init()
844 		gb_tiling_config |= R600_PIPE_TILING(1);  in r600_gfx_init()
847 		gb_tiling_config |= R600_PIPE_TILING(2);  in r600_gfx_init()
850 		gb_tiling_config |= R600_PIPE_TILING(3);  in r600_gfx_init()
856 	gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);  in r600_gfx_init()
858 	gb_tiling_config |= R600_GROUP_SIZE(0);  in r600_gfx_init()
861 		gb_tiling_config |= R600_ROW_TILING(3);  in r600_gfx_init()
862 		gb_tiling_config |= R600_SAMPLE_SPLIT(3);  in r600_gfx_init()
864 		gb_tiling_config |=  in r600_gfx_init()
866 		gb_tiling_config |=  in r600_gfx_init()
870 	gb_tiling_config |= R600_BANK_SWAPS(1);  in r600_gfx_init()
887 	gb_tiling_config |= R600_BACKEND_MAP(backend_map);  in r600_gfx_init()
889 	RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);  in r600_gfx_init()
890 	RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));  in r600_gfx_init()
891 	RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));  in r600_gfx_init()
892 	if (gb_tiling_config & 0xc0) {  in r600_gfx_init()
897 	dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);  in r600_gfx_init()
898 	if (gb_tiling_config & 0x30) {  in r600_gfx_init()
1372 	u32 gb_tiling_config = 0;  in r700_gfx_init()  local
1491 		gb_tiling_config |= R600_PIPE_TILING(0);  in r700_gfx_init()
1494 		gb_tiling_config |= R600_PIPE_TILING(1);  in r700_gfx_init()
1497 		gb_tiling_config |= R600_PIPE_TILING(2);  in r700_gfx_init()
1500 		gb_tiling_config |= R600_PIPE_TILING(3);  in r700_gfx_init()
1507 		gb_tiling_config |= R600_BANK_TILING(1);  in r700_gfx_init()
1509 		gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);  in r700_gfx_init()
1511 	gb_tiling_config |= R600_GROUP_SIZE(0);  in r700_gfx_init()
1514 		gb_tiling_config |= R600_ROW_TILING(3);  in r700_gfx_init()
1515 		gb_tiling_config |= R600_SAMPLE_SPLIT(3);  in r700_gfx_init()
1517 		gb_tiling_config |=  in r700_gfx_init()
1519 		gb_tiling_config |=  in r700_gfx_init()
1523 	gb_tiling_config |= R600_BANK_SWAPS(1);  in r700_gfx_init()
1544 	gb_tiling_config |= R600_BACKEND_MAP(backend_map);  in r700_gfx_init()
1546 	RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);  in r700_gfx_init()
1547 	RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));  in r700_gfx_init()
1548 	RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));  in r700_gfx_init()
1549 	if (gb_tiling_config & 0xc0) {  in r700_gfx_init()
1554 	dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);  in r700_gfx_init()
1555 	if (gb_tiling_config & 0x30) {  in r700_gfx_init()