115 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in rs600_page_flip()  local
116 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);  in rs600_page_flip()
121 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rs600_page_flip()
124 	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in rs600_page_flip()
126 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in rs600_page_flip()
131 		if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)  in rs600_page_flip()
139 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rs600_page_flip()
144 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in rs600_page_flip_pending()  local
147 	return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &  in rs600_page_flip_pending()
313 	struct radeon_crtc *radeon_crtc;  in rs600_pm_prepare()  local
318 		radeon_crtc = to_radeon_crtc(crtc);  in rs600_pm_prepare()
319 		if (radeon_crtc->enabled) {  in rs600_pm_prepare()
320 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);  in rs600_pm_prepare()
322 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in rs600_pm_prepare()
331 	struct radeon_crtc *radeon_crtc;  in rs600_pm_finish()  local
336 		radeon_crtc = to_radeon_crtc(crtc);  in rs600_pm_finish()
337 		if (radeon_crtc->enabled) {  in rs600_pm_finish()
338 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);  in rs600_pm_finish()
340 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in rs600_pm_finish()