1912 				   struct radeon_crtc *radeon_crtc,  in dce6_line_buffer_adjust()  argument
1917 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;  in dce6_line_buffer_adjust()
1931 	if (radeon_crtc->base.enabled && mode) {  in dce6_line_buffer_adjust()
1944 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,  in dce6_line_buffer_adjust()
1956 	if (radeon_crtc->base.enabled && mode) {  in dce6_line_buffer_adjust()
2252 					 struct radeon_crtc *radeon_crtc,  in dce6_program_watermarks()  argument
2255 	struct drm_display_mode *mode = &radeon_crtc->base.mode;  in dce6_program_watermarks()
2267 	if (radeon_crtc->base.enabled && num_heads && mode) {  in dce6_program_watermarks()
2296 		wm_high.vsc = radeon_crtc->vsc;  in dce6_program_watermarks()
2298 		if (radeon_crtc->rmx_type != RMX_OFF)  in dce6_program_watermarks()
2323 		wm_low.vsc = radeon_crtc->vsc;  in dce6_program_watermarks()
2325 		if (radeon_crtc->rmx_type != RMX_OFF)  in dce6_program_watermarks()
2361 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in dce6_program_watermarks()
2373 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in dce6_program_watermarks()
2381 		radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);  in dce6_program_watermarks()
2385 	arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);  in dce6_program_watermarks()
2389 	WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);  in dce6_program_watermarks()
2390 	WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,  in dce6_program_watermarks()
2394 	tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);  in dce6_program_watermarks()
2397 	WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);  in dce6_program_watermarks()
2398 	WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,  in dce6_program_watermarks()
2402 	WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);  in dce6_program_watermarks()
2405 	WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);  in dce6_program_watermarks()
2406 	WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);  in dce6_program_watermarks()
2409 	radeon_crtc->line_time = line_time;  in dce6_program_watermarks()
2410 	radeon_crtc->wm_high = latency_watermark_a;  in dce6_program_watermarks()
2411 	radeon_crtc->wm_low = latency_watermark_b;  in dce6_program_watermarks()