Lines Matching refs:mclk
2996 u32 mclk, sclk; in si_apply_state_adjust_rules() local
3087 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3088 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3112 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3113 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3116 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3117 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3120 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3121 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3132 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3135 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3150 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3151 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3156 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3180 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3182 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3183 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3186 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3191 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3192 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3209 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3212 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3910 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in si_get_strobe_mode_settings() argument
3916 if (mclk <= pi->mclk_strobe_mode_threshold) in si_get_strobe_mode_settings()
3920 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); in si_get_strobe_mode_settings()
3922 result = si_get_ddr3_mclk_frequency_ratio(mclk); in si_get_strobe_mode_settings()
4181 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in si_populate_mvdd_value() argument
4188 if (mclk <= pi->mvdd_split_frequency) in si_populate_mvdd_value()
4261 u16 voltage, u32 sclk, u32 mclk, in si_populate_phase_shedding_value() argument
4269 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
4356 pl->mclk); in si_populate_memory_timing_parameters()
4427 table->initialState.levels[0].mclk.vDLL_CNTL = in si_populate_smc_initial_state()
4429 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_initial_state()
4431 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_initial_state()
4433 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_initial_state()
4435 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4437 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_initial_state()
4439 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4441 table->initialState.levels[0].mclk.vMPLL_SS = in si_populate_smc_initial_state()
4443 table->initialState.levels[0].mclk.vMPLL_SS2 = in si_populate_smc_initial_state()
4446 table->initialState.levels[0].mclk.mclk_value = in si_populate_smc_initial_state()
4447 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4497 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4512 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4514 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
4629 table->ACPIState.levels[0].mclk.vDLL_CNTL = in si_populate_smc_acpi_state()
4631 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_acpi_state()
4633 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_acpi_state()
4635 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_acpi_state()
4637 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
4639 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_acpi_state()
4641 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
4643 table->ACPIState.levels[0].mclk.vMPLL_SS = in si_populate_smc_acpi_state()
4645 table->ACPIState.levels[0].mclk.vMPLL_SS2 = in si_populate_smc_acpi_state()
4657 table->ACPIState.levels[0].mclk.mclk_value = 0; in si_populate_smc_acpi_state()
4926 SISLANDS_SMC_MCLK_VALUE *mclk, in si_populate_mclk_value() argument
4998 mclk->mclk_value = cpu_to_be32(memory_clock); in si_populate_mclk_value()
4999 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in si_populate_mclk_value()
5000 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); in si_populate_mclk_value()
5001 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); in si_populate_mclk_value()
5002 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in si_populate_mclk_value()
5003 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in si_populate_mclk_value()
5004 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in si_populate_mclk_value()
5005 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); in si_populate_mclk_value()
5006 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); in si_populate_mclk_value()
5007 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); in si_populate_mclk_value()
5052 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in si_convert_power_level_to_smc()
5063 if (pl->mclk > pi->mclk_edc_enable_threshold) in si_convert_power_level_to_smc()
5066 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
5069 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); in si_convert_power_level_to_smc()
5072 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= in si_convert_power_level_to_smc()
5082 pl->mclk); in si_convert_power_level_to_smc()
5089 pl->mclk, in si_convert_power_level_to_smc()
5090 &level->mclk, in si_convert_power_level_to_smc()
5123 pl->mclk, in si_convert_power_level_to_smc()
5131 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5205 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5675 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in si_convert_mc_reg_table_entry_to_smc()
6796 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_pplib_clock_info()
6797 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_pplib_clock_info()
6840 pl->mclk = rdev->clock.default_mclk; in si_parse_pplib_clock_info()
6850 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6932 u32 sclk, mclk; in si_parse_power_table() local
6938 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_power_table()
6939 mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_power_table()
6941 rdev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
7104 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7143 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7179 return pl->mclk; in si_dpm_get_current_mclk()