1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
2990 					struct radeon_ps *rps)  in si_apply_state_adjust_rules()  argument
2992 	struct ni_ps *ps = ni_get_ps(rps);  in si_apply_state_adjust_rules()
3057 	if (rps->vce_active) {  in si_apply_state_adjust_rules()
3058 		rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;  in si_apply_state_adjust_rules()
3059 		rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;  in si_apply_state_adjust_rules()
3060 		si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,  in si_apply_state_adjust_rules()
3063 		rps->evclk = 0;  in si_apply_state_adjust_rules()
3064 		rps->ecclk = 0;  in si_apply_state_adjust_rules()
3071 	if (rps->vclk || rps->dclk) {  in si_apply_state_adjust_rules()
3147 	if (rps->vce_active) {  in si_apply_state_adjust_rules()
3454 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;  in si_dpm_force_performance_level()  local
3455 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_force_performance_level()
6755 					  struct radeon_ps *rps,  in si_parse_pplib_non_clock_info()  argument
6759 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);  in si_parse_pplib_non_clock_info()
6760 	rps->class = le16_to_cpu(non_clock_info->usClassification);  in si_parse_pplib_non_clock_info()
6761 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);  in si_parse_pplib_non_clock_info()
6764 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);  in si_parse_pplib_non_clock_info()
6765 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);  in si_parse_pplib_non_clock_info()
6766 	} else if (r600_is_uvd_state(rps->class, rps->class2)) {  in si_parse_pplib_non_clock_info()
6767 		rps->vclk = RV770_DEFAULT_VCLK_FREQ;  in si_parse_pplib_non_clock_info()
6768 		rps->dclk = RV770_DEFAULT_DCLK_FREQ;  in si_parse_pplib_non_clock_info()
6770 		rps->vclk = 0;  in si_parse_pplib_non_clock_info()
6771 		rps->dclk = 0;  in si_parse_pplib_non_clock_info()
6774 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)  in si_parse_pplib_non_clock_info()
6775 		rdev->pm.dpm.boot_ps = rps;  in si_parse_pplib_non_clock_info()
6776 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)  in si_parse_pplib_non_clock_info()
6777 		rdev->pm.dpm.uvd_ps = rps;  in si_parse_pplib_non_clock_info()
6781 				      struct radeon_ps *rps, int index,  in si_parse_pplib_clock_info()  argument
6787 	struct ni_ps *ps = ni_get_ps(rps);  in si_parse_pplib_clock_info()
6813 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {  in si_parse_pplib_clock_info()
6819 	if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&  in si_parse_pplib_clock_info()
6837 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {  in si_parse_pplib_clock_info()
6847 	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==  in si_parse_pplib_clock_info()
7130 	struct radeon_ps *rps = &eg_pi->current_rps;  in si_dpm_debugfs_print_current_performance_level()  local
7131 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_debugfs_print_current_performance_level()
7141 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in si_dpm_debugfs_print_current_performance_level()
7150 	struct radeon_ps *rps = &eg_pi->current_rps;  in si_dpm_get_current_sclk()  local
7151 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_get_current_sclk()
7168 	struct radeon_ps *rps = &eg_pi->current_rps;  in si_dpm_get_current_mclk()  local
7169 	struct ni_ps *ps = ni_get_ps(rps);  in si_dpm_get_current_mclk()