Lines Matching refs:sor
158 int (*probe)(struct tegra_sor *sor);
159 int (*remove)(struct tegra_sor *sor);
217 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) in tegra_sor_readl() argument
219 return readl(sor->regs + (offset << 2)); in tegra_sor_readl()
222 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
225 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
228 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, in tegra_sor_dp_train_fast() argument
241 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
247 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
253 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
256 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_train_fast()
258 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
262 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
264 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
267 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
271 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
274 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_train_fast()
276 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B); in tegra_sor_dp_train_fast()
287 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
291 err = tegra_dpaux_train(sor->dpaux, link, pattern); in tegra_sor_dp_train_fast()
295 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
299 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
308 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
312 err = tegra_dpaux_train(sor->dpaux, link, pattern); in tegra_sor_dp_train_fast()
323 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
327 err = tegra_dpaux_train(sor->dpaux, link, pattern); in tegra_sor_dp_train_fast()
334 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) in tegra_sor_dp_term_calibrate() argument
339 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
341 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
343 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
345 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
350 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
353 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
357 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
364 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_dp_term_calibrate()
367 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_dp_term_calibrate()
370 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
372 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_dp_term_calibrate()
375 static void tegra_sor_super_update(struct tegra_sor *sor) in tegra_sor_super_update() argument
377 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
378 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); in tegra_sor_super_update()
379 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
382 static void tegra_sor_update(struct tegra_sor *sor) in tegra_sor_update() argument
384 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
385 tegra_sor_writel(sor, 1, SOR_STATE0); in tegra_sor_update()
386 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
389 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_setup_pwm() argument
393 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
396 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
398 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
403 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
408 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
418 static int tegra_sor_attach(struct tegra_sor *sor) in tegra_sor_attach() argument
423 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
426 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
427 tegra_sor_super_update(sor); in tegra_sor_attach()
430 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
432 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
433 tegra_sor_super_update(sor); in tegra_sor_attach()
438 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
448 static int tegra_sor_wakeup(struct tegra_sor *sor) in tegra_sor_wakeup() argument
456 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
468 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_power_up() argument
472 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
474 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
479 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
504 static int tegra_sor_compute_params(struct tegra_sor *sor, in tegra_sor_compute_params() argument
572 static int tegra_sor_calc_config(struct tegra_sor *sor, in tegra_sor_calc_config() argument
601 if (tegra_sor_compute_params(sor, ¶ms, i)) in tegra_sor_calc_config()
620 dev_dbg(sor->dev, in tegra_sor_calc_config()
635 dev_err(sor->dev, in tegra_sor_calc_config()
640 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_calc_config()
658 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_calc_config()
664 static int tegra_sor_detach(struct tegra_sor *sor) in tegra_sor_detach() argument
669 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
671 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
672 tegra_sor_super_update(sor); in tegra_sor_detach()
677 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
686 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
688 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
689 tegra_sor_super_update(sor); in tegra_sor_detach()
692 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
694 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
695 tegra_sor_super_update(sor); in tegra_sor_detach()
700 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
713 static int tegra_sor_power_down(struct tegra_sor *sor) in tegra_sor_power_down() argument
718 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
721 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
726 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
736 err = clk_set_parent(sor->clk, sor->clk_safe); in tegra_sor_power_down()
738 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
740 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_power_down()
743 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_power_down()
748 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
753 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
763 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_power_down()
765 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_power_down()
769 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_power_down()
771 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_power_down()
773 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_power_down()
776 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_power_down()
783 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_crc_wait() argument
790 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
803 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc() local
804 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
816 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
818 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
820 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
822 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
824 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
826 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
828 err = tegra_sor_crc_wait(sor, 100); in tegra_sor_show_crc()
832 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); in tegra_sor_show_crc()
833 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
845 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs() local
846 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
859 tegra_sor_readl(sor, name)) in tegra_sor_show_regs()
988 static int tegra_sor_debugfs_init(struct tegra_sor *sor, in tegra_sor_debugfs_init() argument
991 const char *name = sor->soc->supports_dp ? "sor1" : "sor"; in tegra_sor_debugfs_init()
995 sor->debugfs = debugfs_create_dir(name, minor->debugfs_root); in tegra_sor_debugfs_init()
996 if (!sor->debugfs) in tegra_sor_debugfs_init()
999 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_debugfs_init()
1001 if (!sor->debugfs_files) { in tegra_sor_debugfs_init()
1007 sor->debugfs_files[i].data = sor; in tegra_sor_debugfs_init()
1009 err = drm_debugfs_create_files(sor->debugfs_files, in tegra_sor_debugfs_init()
1011 sor->debugfs, minor); in tegra_sor_debugfs_init()
1015 sor->minor = minor; in tegra_sor_debugfs_init()
1020 kfree(sor->debugfs_files); in tegra_sor_debugfs_init()
1021 sor->debugfs_files = NULL; in tegra_sor_debugfs_init()
1023 debugfs_remove_recursive(sor->debugfs); in tegra_sor_debugfs_init()
1024 sor->debugfs = NULL; in tegra_sor_debugfs_init()
1028 static void tegra_sor_debugfs_exit(struct tegra_sor *sor) in tegra_sor_debugfs_exit() argument
1030 drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), in tegra_sor_debugfs_exit()
1031 sor->minor); in tegra_sor_debugfs_exit()
1032 sor->minor = NULL; in tegra_sor_debugfs_exit()
1034 kfree(sor->debugfs_files); in tegra_sor_debugfs_exit()
1035 sor->debugfs_files = NULL; in tegra_sor_debugfs_exit()
1037 debugfs_remove_recursive(sor->debugfs); in tegra_sor_debugfs_exit()
1038 sor->debugfs = NULL; in tegra_sor_debugfs_exit()
1045 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_detect() local
1047 if (sor->dpaux) in tegra_sor_connector_detect()
1048 return tegra_dpaux_detect(sor->dpaux); in tegra_sor_connector_detect()
1066 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_get_modes() local
1069 if (sor->dpaux) in tegra_sor_connector_get_modes()
1070 tegra_dpaux_enable(sor->dpaux); in tegra_sor_connector_get_modes()
1074 if (sor->dpaux) in tegra_sor_connector_get_modes()
1075 tegra_dpaux_disable(sor->dpaux); in tegra_sor_connector_get_modes()
1101 struct tegra_sor *sor = to_sor(output); in tegra_sor_edp_disable() local
1108 err = tegra_sor_detach(sor); in tegra_sor_edp_disable()
1110 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_edp_disable()
1112 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_edp_disable()
1113 tegra_sor_update(sor); in tegra_sor_edp_disable()
1127 err = tegra_sor_power_down(sor); in tegra_sor_edp_disable()
1129 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_edp_disable()
1131 if (sor->dpaux) { in tegra_sor_edp_disable()
1132 err = tegra_dpaux_disable(sor->dpaux); in tegra_sor_edp_disable()
1134 dev_err(sor->dev, "failed to disable DP: %d\n", err); in tegra_sor_edp_disable()
1139 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); in tegra_sor_edp_disable()
1144 reset_control_assert(sor->rst); in tegra_sor_edp_disable()
1145 clk_disable_unprepare(sor->clk); in tegra_sor_edp_disable()
1196 struct tegra_sor *sor = to_sor(output); in tegra_sor_edp_enable() local
1203 err = clk_prepare_enable(sor->clk); in tegra_sor_edp_enable()
1205 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_edp_enable()
1207 reset_control_deassert(sor->rst); in tegra_sor_edp_enable()
1213 aux = (struct drm_dp_aux *)sor->dpaux; in tegra_sor_edp_enable()
1215 if (sor->dpaux) { in tegra_sor_edp_enable()
1216 err = tegra_dpaux_enable(sor->dpaux); in tegra_sor_edp_enable()
1218 dev_err(sor->dev, "failed to enable DP: %d\n", err); in tegra_sor_edp_enable()
1222 dev_err(sor->dev, "failed to probe eDP link: %d\n", in tegra_sor_edp_enable()
1228 err = clk_set_parent(sor->clk, sor->clk_safe); in tegra_sor_edp_enable()
1230 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_edp_enable()
1235 err = tegra_sor_calc_config(sor, mode, &config, &link); in tegra_sor_edp_enable()
1237 dev_err(sor->dev, "failed to compute link configuration: %d\n", in tegra_sor_edp_enable()
1240 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1243 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1245 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1247 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1250 value = tegra_sor_readl(sor, SOR_PLL3); in tegra_sor_edp_enable()
1252 tegra_sor_writel(sor, value, SOR_PLL3); in tegra_sor_edp_enable()
1256 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1258 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1262 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1265 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_edp_enable()
1268 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1275 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1278 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1285 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1288 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1291 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1294 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1296 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_edp_enable()
1298 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1300 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1302 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1307 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); in tegra_sor_edp_enable()
1312 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1314 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1319 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_edp_enable()
1322 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_edp_enable()
1324 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1326 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1331 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_edp_enable()
1333 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_edp_enable()
1336 err = clk_set_parent(sor->clk, sor->clk_dp); in tegra_sor_edp_enable()
1338 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); in tegra_sor_edp_enable()
1341 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1358 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1360 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1363 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1368 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1371 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1379 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1382 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1385 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1392 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1401 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1403 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_edp_enable()
1420 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_edp_enable()
1422 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_edp_enable()
1425 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_edp_enable()
1427 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_edp_enable()
1430 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_edp_enable()
1433 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1435 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_edp_enable()
1437 if (sor->dpaux) { in tegra_sor_edp_enable()
1442 dev_err(sor->dev, "failed to probe eDP link: %d\n", in tegra_sor_edp_enable()
1447 dev_err(sor->dev, "failed to power up eDP link: %d\n", in tegra_sor_edp_enable()
1452 dev_err(sor->dev, "failed to configure eDP link: %d\n", in tegra_sor_edp_enable()
1458 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1461 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1463 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1470 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1481 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1483 err = tegra_sor_dp_train_fast(sor, &link); in tegra_sor_edp_enable()
1485 dev_err(sor->dev, "DP fast link training failed: %d\n", in tegra_sor_edp_enable()
1489 dev_dbg(sor->dev, "fast link training succeeded\n"); in tegra_sor_edp_enable()
1492 err = tegra_sor_power_up(sor, 250); in tegra_sor_edp_enable()
1494 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_edp_enable()
1530 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_edp_enable()
1538 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); in tegra_sor_edp_enable()
1544 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); in tegra_sor_edp_enable()
1550 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); in tegra_sor_edp_enable()
1556 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); in tegra_sor_edp_enable()
1558 tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe)); in tegra_sor_edp_enable()
1563 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_edp_enable()
1566 err = tegra_sor_setup_pwm(sor, 250); in tegra_sor_edp_enable()
1568 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_edp_enable()
1570 tegra_sor_update(sor); in tegra_sor_edp_enable()
1578 err = tegra_sor_attach(sor); in tegra_sor_edp_enable()
1580 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_edp_enable()
1582 err = tegra_sor_wakeup(sor); in tegra_sor_edp_enable()
1584 dev_err(sor->dev, "failed to enable DC: %d\n", err); in tegra_sor_edp_enable()
1598 struct tegra_sor *sor = to_sor(output); in tegra_sor_encoder_atomic_check() local
1601 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
1628 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, in tegra_sor_hdmi_write_infopack() argument
1650 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
1658 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1670 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1675 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1680 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, in tegra_sor_hdmi_setup_avi_infoframe() argument
1689 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1693 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1697 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1703 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1707 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_setup_avi_infoframe()
1710 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1713 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1718 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_disable_audio_infoframe() argument
1722 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
1724 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
1728 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) in tegra_sor_hdmi_find_settings() argument
1732 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
1733 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
1734 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
1743 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_disable() local
1747 err = tegra_sor_detach(sor); in tegra_sor_hdmi_disable()
1749 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
1751 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
1752 tegra_sor_update(sor); in tegra_sor_hdmi_disable()
1762 err = tegra_sor_power_down(sor); in tegra_sor_hdmi_disable()
1764 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
1768 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err); in tegra_sor_hdmi_disable()
1770 reset_control_assert(sor->rst); in tegra_sor_hdmi_disable()
1772 clk_disable_unprepare(sor->clk); in tegra_sor_hdmi_disable()
1782 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_enable() local
1791 err = clk_prepare_enable(sor->clk); in tegra_sor_hdmi_enable()
1793 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_hdmi_enable()
1797 reset_control_deassert(sor->rst); in tegra_sor_hdmi_enable()
1799 err = clk_set_parent(sor->clk, sor->clk_safe); in tegra_sor_hdmi_enable()
1801 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
1803 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
1807 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err); in tegra_sor_hdmi_enable()
1811 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_hdmi_enable()
1813 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_hdmi_enable()
1817 value = tegra_sor_readl(sor, SOR_PLL3); in tegra_sor_hdmi_enable()
1819 tegra_sor_writel(sor, value, SOR_PLL3); in tegra_sor_hdmi_enable()
1821 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_hdmi_enable()
1824 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_hdmi_enable()
1826 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_hdmi_enable()
1828 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_hdmi_enable()
1832 value = tegra_sor_readl(sor, SOR_PLL2); in tegra_sor_hdmi_enable()
1835 tegra_sor_writel(sor, value, SOR_PLL2); in tegra_sor_hdmi_enable()
1839 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1842 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1845 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
1854 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
1857 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
1864 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
1874 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
1876 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
1880 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
1884 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
1888 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
1889 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
1893 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
1906 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
1908 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
1910 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
1912 dev_err(sor->dev, "failed to set parent clock: %d\n", err); in tegra_sor_hdmi_enable()
1920 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
1926 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
1944 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); in tegra_sor_hdmi_enable()
1946 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
1949 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_enable()
1952 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
1955 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
1958 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1960 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
1963 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
1965 dev_err(sor->dev, "no settings for pixel clock %d Hz: %ld\n", in tegra_sor_hdmi_enable()
1970 value = tegra_sor_readl(sor, SOR_PLL0); in tegra_sor_hdmi_enable()
1975 tegra_sor_writel(sor, value, SOR_PLL0); in tegra_sor_hdmi_enable()
1977 tegra_sor_dp_term_calibrate(sor); in tegra_sor_hdmi_enable()
1979 value = tegra_sor_readl(sor, SOR_PLL1); in tegra_sor_hdmi_enable()
1982 tegra_sor_writel(sor, value, SOR_PLL1); in tegra_sor_hdmi_enable()
1984 value = tegra_sor_readl(sor, SOR_PLL3); in tegra_sor_hdmi_enable()
1987 tegra_sor_writel(sor, value, SOR_PLL3); in tegra_sor_hdmi_enable()
1993 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
1999 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2001 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2005 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2008 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2010 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); in tegra_sor_hdmi_enable()
2036 err = tegra_sor_power_up(sor, 250); in tegra_sor_hdmi_enable()
2038 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2041 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2075 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2077 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2080 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2082 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2085 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); in tegra_sor_hdmi_enable()
2093 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); in tegra_sor_hdmi_enable()
2100 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); in tegra_sor_hdmi_enable()
2107 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); in tegra_sor_hdmi_enable()
2114 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); in tegra_sor_hdmi_enable()
2116 tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe)); in tegra_sor_hdmi_enable()
2118 tegra_sor_update(sor); in tegra_sor_hdmi_enable()
2120 err = tegra_sor_attach(sor); in tegra_sor_hdmi_enable()
2122 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2131 err = tegra_sor_wakeup(sor); in tegra_sor_hdmi_enable()
2133 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2146 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_init() local
2151 if (!sor->dpaux) { in tegra_sor_init()
2152 if (sor->soc->supports_hdmi) { in tegra_sor_init()
2156 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
2161 if (sor->soc->supports_edp) { in tegra_sor_init()
2165 } else if (sor->soc->supports_dp) { in tegra_sor_init()
2171 sor->output.dev = sor->dev; in tegra_sor_init()
2173 drm_connector_init(drm, &sor->output.connector, in tegra_sor_init()
2176 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
2178 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
2180 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, in tegra_sor_init()
2182 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
2184 drm_mode_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
2185 &sor->output.encoder); in tegra_sor_init()
2186 drm_connector_register(&sor->output.connector); in tegra_sor_init()
2188 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
2194 sor->output.encoder.possible_crtcs = 0x3; in tegra_sor_init()
2197 err = tegra_sor_debugfs_init(sor, drm->primary); in tegra_sor_init()
2199 dev_err(sor->dev, "debugfs setup failed: %d\n", err); in tegra_sor_init()
2202 if (sor->dpaux) { in tegra_sor_init()
2203 err = tegra_dpaux_attach(sor->dpaux, &sor->output); in tegra_sor_init()
2205 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
2214 err = reset_control_assert(sor->rst); in tegra_sor_init()
2216 dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); in tegra_sor_init()
2220 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
2222 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
2228 err = reset_control_deassert(sor->rst); in tegra_sor_init()
2230 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); in tegra_sor_init()
2234 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
2238 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
2247 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_exit() local
2250 tegra_output_exit(&sor->output); in tegra_sor_exit()
2252 if (sor->dpaux) { in tegra_sor_exit()
2253 err = tegra_dpaux_detach(sor->dpaux); in tegra_sor_exit()
2255 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
2260 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
2261 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
2262 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
2265 tegra_sor_debugfs_exit(sor); in tegra_sor_exit()
2279 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) in tegra_sor_hdmi_probe() argument
2283 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); in tegra_sor_hdmi_probe()
2284 if (IS_ERR(sor->avdd_io_supply)) { in tegra_sor_hdmi_probe()
2285 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", in tegra_sor_hdmi_probe()
2286 PTR_ERR(sor->avdd_io_supply)); in tegra_sor_hdmi_probe()
2287 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2290 err = regulator_enable(sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2292 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2297 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); in tegra_sor_hdmi_probe()
2298 if (IS_ERR(sor->vdd_pll_supply)) { in tegra_sor_hdmi_probe()
2299 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", in tegra_sor_hdmi_probe()
2300 PTR_ERR(sor->vdd_pll_supply)); in tegra_sor_hdmi_probe()
2301 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2304 err = regulator_enable(sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2306 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2311 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2312 if (IS_ERR(sor->hdmi_supply)) { in tegra_sor_hdmi_probe()
2313 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", in tegra_sor_hdmi_probe()
2314 PTR_ERR(sor->hdmi_supply)); in tegra_sor_hdmi_probe()
2315 return PTR_ERR(sor->hdmi_supply); in tegra_sor_hdmi_probe()
2318 err = regulator_enable(sor->hdmi_supply); in tegra_sor_hdmi_probe()
2320 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
2327 static int tegra_sor_hdmi_remove(struct tegra_sor *sor) in tegra_sor_hdmi_remove() argument
2329 regulator_disable(sor->hdmi_supply); in tegra_sor_hdmi_remove()
2330 regulator_disable(sor->vdd_pll_supply); in tegra_sor_hdmi_remove()
2331 regulator_disable(sor->avdd_io_supply); in tegra_sor_hdmi_remove()
2378 struct tegra_sor *sor; in tegra_sor_probe() local
2384 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
2385 if (!sor) in tegra_sor_probe()
2388 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
2389 sor->soc = match->data; in tegra_sor_probe()
2391 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
2392 sor->soc->num_settings * in tegra_sor_probe()
2393 sizeof(*sor->settings), in tegra_sor_probe()
2395 if (!sor->settings) in tegra_sor_probe()
2398 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
2402 sor->dpaux = tegra_dpaux_find_by_of_node(np); in tegra_sor_probe()
2405 if (!sor->dpaux) in tegra_sor_probe()
2409 if (!sor->dpaux) { in tegra_sor_probe()
2410 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
2411 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
2412 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
2420 if (sor->soc->supports_edp) { in tegra_sor_probe()
2421 sor->ops = &tegra_sor_edp_ops; in tegra_sor_probe()
2422 } else if (sor->soc->supports_dp) { in tegra_sor_probe()
2431 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
2437 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
2438 err = sor->ops->probe(sor); in tegra_sor_probe()
2441 sor->ops->name, err); in tegra_sor_probe()
2447 sor->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_sor_probe()
2448 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
2449 err = PTR_ERR(sor->regs); in tegra_sor_probe()
2453 sor->rst = devm_reset_control_get(&pdev->dev, "sor"); in tegra_sor_probe()
2454 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
2455 err = PTR_ERR(sor->rst); in tegra_sor_probe()
2460 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
2461 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
2462 err = PTR_ERR(sor->clk); in tegra_sor_probe()
2467 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
2468 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
2469 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
2474 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
2475 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
2476 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
2481 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
2482 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
2483 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
2488 INIT_LIST_HEAD(&sor->client.list); in tegra_sor_probe()
2489 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
2490 sor->client.dev = &pdev->dev; in tegra_sor_probe()
2492 err = host1x_client_register(&sor->client); in tegra_sor_probe()
2499 platform_set_drvdata(pdev, sor); in tegra_sor_probe()
2504 if (sor->ops && sor->ops->remove) in tegra_sor_probe()
2505 sor->ops->remove(sor); in tegra_sor_probe()
2507 tegra_output_remove(&sor->output); in tegra_sor_probe()
2513 struct tegra_sor *sor = platform_get_drvdata(pdev); in tegra_sor_remove() local
2516 err = host1x_client_unregister(&sor->client); in tegra_sor_remove()
2523 if (sor->ops && sor->ops->remove) { in tegra_sor_remove()
2524 err = sor->ops->remove(sor); in tegra_sor_remove()
2529 tegra_output_remove(&sor->output); in tegra_sor_remove()