Lines Matching refs:njet
101 return (inb(cs->hw.njet.isac + 4 * offset)); in ReadByteAmd7930()
105 outb(offset, cs->hw.njet.isac + 4 * AMD_CR); in ReadByteAmd7930()
106 return (inb(cs->hw.njet.isac + 4 * AMD_DR)); in ReadByteAmd7930()
116 outb(value, cs->hw.njet.isac + 4 * offset); in WriteByteAmd7930()
120 outb(offset, cs->hw.njet.isac + 4 * AMD_CR); in WriteByteAmd7930()
121 outb(value, cs->hw.njet.isac + 4 * AMD_DR); in WriteByteAmd7930()
129 outb(0x00, cs->hw.njet.base + NETJET_IRQMASK1); in enpci_setIrqMask()
131 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); in enpci_setIrqMask()
156 cs->hw.njet.ctrl_reg = 0x07; in reset_enpci()
157 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in reset_enpci()
160 cs->hw.njet.ctrl_reg = 0x30; in reset_enpci()
161 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in reset_enpci()
164 cs->hw.njet.auxd = 0; // LED-status in reset_enpci()
165 cs->hw.njet.dmactrl = 0; in reset_enpci()
166 outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL); in reset_enpci()
167 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); in reset_enpci()
168 outb(cs->hw.njet.auxd, cs->hw.njet.auxa); // LED off in reset_enpci()
201 cs->hw.njet.auxd = TJ_AMD_IRQ << 1; in enpci_card_msg()
202 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); in enpci_card_msg()
206 cs->hw.njet.auxd = 0; in enpci_card_msg()
207 outb(0x00, cs->hw.njet.base + NETJET_AUXDATA); in enpci_card_msg()
218 cs->hw.njet.auxd |= TJ_AMD_IRQ << 2; in enpci_card_msg()
219 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); in enpci_card_msg()
231 cs->hw.njet.auxd &= ~(TJ_AMD_IRQ << 2); in enpci_card_msg()
232 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); in enpci_card_msg()
250 s1val = inb(cs->hw.njet.base + NETJET_IRQSTAT1); in enpci_interrupt()
260 s0val = inb(cs->hw.njet.base + NETJET_IRQSTAT0); in enpci_interrupt()
266 outb(s0val, cs->hw.njet.base + NETJET_IRQSTAT0); in enpci_interrupt()
270 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) < in enpci_interrupt()
271 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ)) in enpci_interrupt()
276 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) < in enpci_interrupt()
277 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ)) in enpci_interrupt()
282 if (s0val != cs->hw.njet.last_is0) /* we have a DMA interrupt */ in enpci_interrupt()
288 cs->hw.njet.irqstat0 = s0val; in enpci_interrupt()
289 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) != in enpci_interrupt()
290 (cs->hw.njet.last_is0 & NETJET_IRQM0_READ)) in enpci_interrupt()
293 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) != in enpci_interrupt()
294 (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE)) in enpci_interrupt()
312 cs->hw.njet.base = pci_resource_start(dev_netjet, 0); in en_pci_probe()
313 if (!cs->hw.njet.base) { in en_pci_probe()
330 cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA; in en_cs_init()
331 cs->hw.njet.isac = cs->hw.njet.base + 0xC0; // Fenster zum AMD in en_cs_init()
334 cs->hw.njet.ctrl_reg = 0x07; // geändert von 0xff in en_cs_init()
335 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in en_cs_init()
339 cs->hw.njet.ctrl_reg = 0x30; /* Reset Off and status read clear */ in en_cs_init()
340 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in en_cs_init()
343 cs->hw.njet.auxd = 0x00; // war 0xc0 in en_cs_init()
344 cs->hw.njet.dmactrl = 0; in en_cs_init()
346 outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL); in en_cs_init()
347 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); in en_cs_init()
348 outb(cs->hw.njet.auxd, cs->hw.njet.auxa); in en_cs_init()
357 cs->hw.njet.base, cs->irq); in en_cs_init_rest()
358 if (!request_region(cs->hw.njet.base, bytecnt, "Fn_ISDN")) { in en_cs_init_rest()
361 cs->hw.njet.base, in en_cs_init_rest()
362 cs->hw.njet.base + bytecnt); in en_cs_init_rest()
367 cs->hw.njet.last_is0 = 0; in en_cs_init_rest()