103 	cx_write(MO_TS_LNGTH, dev->ts_packet_size);  in cx8802_start_dma()
115 		cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);  in cx8802_start_dma()
117 		cx_write(MO_PINMUX_IO, 0x00);  in cx8802_start_dma()
118 		cx_write(TS_HW_SOP_CNTRL, 0x47<<16|188<<4|0x01);  in cx8802_start_dma()
124 			cx_write(TS_SOP_STAT, 1<<13);  in cx8802_start_dma()
127 			cx_write(TS_SOP_STAT, 0x00);  in cx8802_start_dma()
131 			cx_write(MO_PINMUX_IO, 0x88); /* Enable MPEG parallel IO and video signal pins */  in cx8802_start_dma()
136 			cx_write(MO_PINMUX_IO, 0x88);  in cx8802_start_dma()
137 			cx_write(TS_SOP_STAT, 0);  in cx8802_start_dma()
138 			cx_write(TS_VALERR_CNTRL, 0);  in cx8802_start_dma()
142 			cx_write(MO_PINMUX_IO, 0x88);  in cx8802_start_dma()
143 			cx_write(TS_HW_SOP_CNTRL, (0x47 << 16) | (188 << 4));  in cx8802_start_dma()
145 			cx_write(TS_SOP_STAT, 0);  in cx8802_start_dma()
146 			cx_write(TS_VALERR_CNTRL, 0);  in cx8802_start_dma()
150 			cx_write(TS_SOP_STAT, 0x00);  in cx8802_start_dma()
153 		cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);  in cx8802_start_dma()
158 		cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */  in cx8802_start_dma()
160 		cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */  in cx8802_start_dma()
163 		cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */  in cx8802_start_dma()
164 		cx_write(TS_VALERR_CNTRL, 0x2000);  in cx8802_start_dma()
166 		cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */  in cx8802_start_dma()
175 	cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);  in cx8802_start_dma()
202 	cx_write(TS_GEN_CNTRL, 0xcd);  in cx8802_stop_dma()
319 	cx_write(MO_TS_INTSTAT, status);  in cx8802_mpeg_irq()
369 		cx_write(MO_PCI_INTSTAT, status);  in cx8802_irq()
380 		cx_write(MO_PCI_INTMSK,0);  in cx8802_irq()