106 	if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags))  in ivtv_irq_work_handler()
109 	if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags))  in ivtv_irq_work_handler()
112 	if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags))  in ivtv_irq_work_handler()
115 	if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_PCM, &itv->i_flags))  in ivtv_irq_work_handler()
341 		set_bit(IVTV_F_I_WORK_HANDLER_PCM, &itv->i_flags);  in dma_post()
342 		set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);  in dma_post()
413 		if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))  in ivtv_dma_stream_dec_prepare()
419 		if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))  in ivtv_dma_stream_dec_prepare()
507 		set_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags);  in ivtv_dma_enc_start()
508 		set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);  in ivtv_dma_enc_start()
509 		set_bit(IVTV_F_I_PIO, &itv->i_flags);  in ivtv_dma_enc_start()
515 		set_bit(IVTV_F_I_DMA, &itv->i_flags);  in ivtv_dma_enc_start()
535 	set_bit(IVTV_F_I_DMA, &itv->i_flags);  in ivtv_dma_dec_start()
549 	if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) && itv->cur_dma_stream < 0)  in ivtv_irq_dma_read()
552 	if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {  in ivtv_irq_dma_read()
598 	clear_bit(IVTV_F_I_UDMA, &itv->i_flags);  in ivtv_irq_dma_read()
599 	clear_bit(IVTV_F_I_DMA, &itv->i_flags);  in ivtv_irq_dma_read()
641 	clear_bit(IVTV_F_I_DMA, &itv->i_flags);  in ivtv_irq_enc_dma_complete()
663 	clear_bit(IVTV_F_I_PIO, &itv->i_flags);  in ivtv_irq_enc_pio_complete()
672 	clear_bit(IVTV_F_I_PIO, &itv->i_flags);  in ivtv_irq_enc_pio_complete()
704 	if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) &&  in ivtv_irq_dma_err()
744 	if (test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {  in ivtv_irq_dma_err()
748 	clear_bit(IVTV_F_I_UDMA, &itv->i_flags);  in ivtv_irq_dma_err()
749 	clear_bit(IVTV_F_I_DMA, &itv->i_flags);  in ivtv_irq_dma_err()
805 	if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) {  in ivtv_irq_dec_data_req()
826 		if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags))  in ivtv_irq_dec_data_req()
881 			clear_bit(IVTV_F_I_VALID_DEC_TIMINGS, &itv->i_flags);  in ivtv_irq_vsync()
882 			clear_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);  in ivtv_irq_vsync()
885 			set_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);  in ivtv_irq_vsync()
887 		if (test_bit(IVTV_F_I_EV_VSYNC_ENABLED, &itv->i_flags)) {  in ivtv_irq_vsync()
888 			set_bit(IVTV_F_I_EV_VSYNC, &itv->i_flags);  in ivtv_irq_vsync()
899 			test_bit(IVTV_F_I_UPDATE_WSS, &itv->i_flags) ||  in ivtv_irq_vsync()
900 			test_bit(IVTV_F_I_UPDATE_VPS, &itv->i_flags) ||  in ivtv_irq_vsync()
901 			test_bit(IVTV_F_I_UPDATE_CC, &itv->i_flags))) {  in ivtv_irq_vsync()
902 			set_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags);  in ivtv_irq_vsync()
903 			set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);  in ivtv_irq_vsync()
919 				set_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags);  in ivtv_irq_vsync()
920 				set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);  in ivtv_irq_vsync()
1008 		set_bit(IVTV_F_I_EOS, &itv->i_flags);  in ivtv_irq_handler()
1030 	if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_DMA, &itv->i_flags)) {  in ivtv_irq_handler()
1046 		    test_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags))  in ivtv_irq_handler()
1050 	if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_PIO, &itv->i_flags)) {  in ivtv_irq_handler()
1064 	if (test_and_clear_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags)) {  in ivtv_irq_handler()
1081 	if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))  in ivtv_unfinished_dma()
1086 	clear_bit(IVTV_F_I_UDMA, &itv->i_flags);  in ivtv_unfinished_dma()
1087 	clear_bit(IVTV_F_I_DMA, &itv->i_flags);  in ivtv_unfinished_dma()