Lines Matching refs:mclk
392 unsigned long mclk; member
408 unsigned long mclk, in sm501_calc_clock() argument
423 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq; in sm501_calc_clock()
431 clock->mclk = mclk; in sm501_calc_clock()
453 unsigned long mclk; in sm501_calc_pll() local
464 mclk = (24000000UL * m / n) >> k; in sm501_calc_pll()
467 mclk, &best_diff)) { in sm501_calc_pll()
477 return clock->mclk / (clock->divider << clock->shift); in sm501_calc_pll()
491 unsigned long mclk; in sm501_select_clock() local
495 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { in sm501_select_clock()
496 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff); in sm501_select_clock()
500 return clock->mclk / (clock->divider << clock->shift); in sm501_select_clock()
552 if (to.mclk != 288000000) in sm501_set_clock()
565 if (to.mclk != 288000000) in sm501_set_clock()
577 if (to.mclk != 288000000) in sm501_set_clock()
1268 if (init->mclk) { in sm501_init_regs()
1269 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); in sm501_init_regs()
1270 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk); in sm501_init_regs()
1554 .mclk = 72 * MHZ,