Lines Matching refs:CSR0

150 #define CSR0  0x00  macro
166 #define writedatareg(val) {  writereg(val,CSR0); }
171 #define writedatareg(val) { writereg(val,CSR0); }
273 	writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */  in ni65_set_performance()
288 	outw(CSR0,PORT+L_ADDRREG);	/* switch back to CSR0 */  in ni65_set_performance()
464 	if( (j=readreg(CSR0)) != 0x4) {  in ni65_probe1()
516 				if(readreg(CSR0) & CSR0_IDON)  in ni65_probe1()
538 			writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */  in ni65_probe1()
577 	writereg(CSR0_CLRALL|CSR0_STOP,CSR0);  in ni65_init_lance()
593 	writereg(CSR0_INIT,CSR0); /* this changes L_ADDRREG to CSR0 */  in ni65_init_lance()
810 	 if( (i=readreg(CSR0) ) != 0x4)  in ni65_lance_reinit()