32 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)  in xgene_set_bits()  argument
37 	*dst &= ~mask;  in xgene_set_bits()
38 	*dst |= (val << start) & mask;  in xgene_set_bits()
128 #define PHY_CONTROL_SET(dst, val)	xgene_set_bits(dst, val, 0, 16)  argument
146 #define CFG_TXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 29, 3)  argument
147 #define CFG_RXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 26, 3)  argument
149 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val)	xgene_set_bits(dst, val, 16, 2)  argument
150 #define CFG_CLE_IP_HDR_LEN_SET(dst, val)	xgene_set_bits(dst, val, 8, 5)  argument
151 #define CFG_CLE_DSTQID0_SET(dst, val)		xgene_set_bits(dst, val, 0, 12)  argument
152 #define CFG_CLE_FPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 16, 4)  argument
153 #define CFG_MACMODE_SET(dst, val)		xgene_set_bits(dst, val, 18, 2)  argument
154 #define CFG_WAITASYNCRD_SET(dst, val)		xgene_set_bits(dst, val, 0, 16)  argument
175 #define PHY_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 8, 5)  argument
176 #define REG_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 0, 5)  argument
177 #define ENET_INTERFACE_MODE2_SET(dst, val)	xgene_set_bits(dst, val, 8, 2)  argument
178 #define MGMT_CLOCK_SEL_SET(dst, val)		xgene_set_bits(dst, val, 0, 3)  argument