Lines Matching refs:octeon_write_csr64

45 	octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF);  in lio_cn6xxx_soft_reset()
50 	octeon_write_csr64(oct, CN6XXX_SLI_SCRATCH1, 0x1234ULL);  in lio_cn6xxx_soft_reset()
67 	octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF);  in lio_cn6xxx_soft_reset()
131 	octeon_write_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port), r64);  in lio_cn6xxx_setup_pcie_mrrs()
179 	octeon_write_csr64(oct, CN6XXX_SLI_PKT_INSTR_RD_SIZE,  in lio_cn6xxx_setup_global_input_regs()
183 	octeon_write_csr64(oct, CN6XXX_SLI_IN_PCIE_PORT,  in lio_cn6xxx_setup_global_input_regs()
207 	octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl);  in lio_cn66xx_setup_pkt_ctl_regs()
216 	octeon_write_csr64(oct, CN6XXX_SLI_PKT_PCIE_PORT64,  in lio_cn6xxx_setup_global_output_regs()
220 		octeon_write_csr64(oct, CN6XXX_SLI_OQ_WMARK, 32);  in lio_cn6xxx_setup_global_output_regs()
223 		octeon_write_csr64(oct, CN6XXX_SLI_OQ_WMARK, 0);  in lio_cn6xxx_setup_global_output_regs()
245 	octeon_write_csr64(oct, CN6XXX_SLI_PKT_SLIST_ES64,  in lio_cn6xxx_setup_global_output_regs()
248 	octeon_write_csr64(oct, CN6XXX_SLI_PKT_SLIST_ES64, 0ULL);  in lio_cn6xxx_setup_global_output_regs()
254 	octeon_write_csr64(oct, CN6XXX_SLI_PKT_DATA_OUT_ES64,  in lio_cn6xxx_setup_global_output_regs()
280 	octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL);  in lio_cn6xxx_setup_device_regs()
289 	octeon_write_csr64(oct, CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq_no), 0);  in lio_cn6xxx_setup_iq_regs()
292 	octeon_write_csr64(oct, CN6XXX_SLI_IQ_BASE_ADDR64(iq_no),  in lio_cn6xxx_setup_iq_regs()
318 	octeon_write_csr64(oct, CN66XX_SLI_IQ_BP64(iq_no),  in lio_cn66xx_setup_iq_regs()
327 	octeon_write_csr64(oct, CN6XXX_SLI_OQ_BASE_ADDR64(oq_no),  in lio_cn6xxx_setup_oq_regs()