Lines Matching refs:pe
1018 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
1022 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
1026 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
1029 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1031 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1034 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1036 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1042 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_read() argument
1046 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_read()
1050 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1052 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_hw_read()
1054 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_hw_read()
1058 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1061 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1063 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1093 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument
1097 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; in mvpp2_prs_tcam_lu_set()
1098 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; in mvpp2_prs_tcam_lu_set()
1102 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_set() argument
1108 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1110 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1114 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_map_set() argument
1120 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; in mvpp2_prs_tcam_port_map_set()
1121 pe->tcam.byte[enable_off] &= ~port_mask; in mvpp2_prs_tcam_port_map_set()
1122 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_set()
1126 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_port_map_get() argument
1130 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
1134 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_set() argument
1138 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; in mvpp2_prs_tcam_data_byte_set()
1139 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; in mvpp2_prs_tcam_data_byte_set()
1143 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_get() argument
1147 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; in mvpp2_prs_tcam_data_byte_get()
1148 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; in mvpp2_prs_tcam_data_byte_get()
1152 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, in mvpp2_prs_tcam_data_cmp() argument
1158 tcam_data = (8 << pe->tcam.byte[off + 1]) | pe->tcam.byte[off]; in mvpp2_prs_tcam_data_cmp()
1165 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_ai_update() argument
1176 pe->tcam.byte[ai_idx] |= 1 << i; in mvpp2_prs_tcam_ai_update()
1178 pe->tcam.byte[ai_idx] &= ~(1 << i); in mvpp2_prs_tcam_ai_update()
1181 pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable; in mvpp2_prs_tcam_ai_update()
1185 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_ai_get() argument
1187 return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE]; in mvpp2_prs_tcam_ai_get()
1191 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_etype() argument
1194 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); in mvpp2_prs_match_etype()
1195 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); in mvpp2_prs_match_etype()
1199 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_set() argument
1202 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); in mvpp2_prs_sram_bits_set()
1206 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_clear() argument
1209 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); in mvpp2_prs_sram_bits_clear()
1213 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ri_update() argument
1225 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1227 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1229 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ri_update()
1234 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ri_get() argument
1236 return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD]; in mvpp2_prs_sram_ri_get()
1240 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ai_update() argument
1252 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1254 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1256 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ai_update()
1261 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ai_get() argument
1268 bits = (pe->sram.byte[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
1269 (pe->sram.byte[ai_en_off] << (8 - ai_shift)); in mvpp2_prs_sram_ai_get()
1277 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_next_lu_set() argument
1282 mvpp2_prs_sram_bits_clear(pe, sram_next_off, in mvpp2_prs_sram_next_lu_set()
1284 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set()
1290 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, in mvpp2_prs_sram_shift_set() argument
1295 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1298 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1302 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = in mvpp2_prs_sram_shift_set()
1306 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, in mvpp2_prs_sram_shift_set()
1308 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); in mvpp2_prs_sram_shift_set()
1311 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_shift_set()
1317 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_offset_set() argument
1323 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1326 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1330 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1332 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); in mvpp2_prs_sram_offset_set()
1333 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1336 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1341 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, in mvpp2_prs_sram_offset_set()
1343 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); in mvpp2_prs_sram_offset_set()
1346 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1348 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); in mvpp2_prs_sram_offset_set()
1350 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1355 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1360 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_offset_set()
1366 struct mvpp2_prs_entry *pe; in mvpp2_prs_flow_find() local
1369 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_flow_find()
1370 if (!pe) in mvpp2_prs_flow_find()
1372 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_flow_find()
1382 pe->index = tid; in mvpp2_prs_flow_find()
1383 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_flow_find()
1384 bits = mvpp2_prs_sram_ai_get(pe); in mvpp2_prs_flow_find()
1388 return pe; in mvpp2_prs_flow_find()
1390 kfree(pe); in mvpp2_prs_flow_find()
1418 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_drop_all_set() local
1422 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1423 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1426 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_drop_all_set()
1427 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1428 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1431 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_drop_all_set()
1434 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_drop_all_set()
1435 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_drop_all_set()
1438 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1441 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_drop_all_set()
1445 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1447 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1453 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_promisc_set() local
1459 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1460 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_promisc_set()
1463 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_promisc_set()
1464 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1465 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1468 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_promisc_set()
1471 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, in mvpp2_prs_mac_promisc_set()
1475 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_promisc_set()
1479 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_promisc_set()
1482 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1486 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1488 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_promisc_set()
1495 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_multi_set() local
1505 pe.index = index; in mvpp2_prs_mac_multi_set()
1506 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_multi_set()
1509 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_multi_set()
1510 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1511 pe.index = index; in mvpp2_prs_mac_multi_set()
1514 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_multi_set()
1517 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST, in mvpp2_prs_mac_multi_set()
1521 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff); in mvpp2_prs_mac_multi_set()
1524 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_multi_set()
1528 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_multi_set()
1531 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1535 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1537 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_multi_set()
1544 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_set() local
1557 pe.index = tid; in mvpp2_prs_dsa_tag_set()
1558 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_dsa_tag_set()
1561 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_dsa_tag_set()
1562 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
1563 pe.index = tid; in mvpp2_prs_dsa_tag_set()
1566 mvpp2_prs_sram_shift_set(&pe, shift, in mvpp2_prs_dsa_tag_set()
1570 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
1574 mvpp2_prs_tcam_data_byte_set(&pe, 0, in mvpp2_prs_dsa_tag_set()
1578 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_set()
1581 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_set()
1584 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_set()
1586 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_set()
1590 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_dsa_tag_set()
1594 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_set()
1596 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_set()
1603 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_ethertype_set() local
1620 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
1621 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
1624 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_dsa_tag_ethertype_set()
1625 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
1626 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
1629 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); in mvpp2_prs_dsa_tag_ethertype_set()
1630 mvpp2_prs_match_etype(&pe, 2, 0); in mvpp2_prs_dsa_tag_ethertype_set()
1632 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, in mvpp2_prs_dsa_tag_ethertype_set()
1635 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, in mvpp2_prs_dsa_tag_ethertype_set()
1639 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
1643 mvpp2_prs_tcam_data_byte_set(&pe, in mvpp2_prs_dsa_tag_ethertype_set()
1648 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_ethertype_set()
1651 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_ethertype_set()
1654 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_ethertype_set()
1656 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_ethertype_set()
1659 mvpp2_prs_tcam_port_map_set(&pe, port_mask); in mvpp2_prs_dsa_tag_ethertype_set()
1663 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_ethertype_set()
1665 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
1672 struct mvpp2_prs_entry *pe; in mvpp2_prs_vlan_find() local
1675 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_vlan_find()
1676 if (!pe) in mvpp2_prs_vlan_find()
1678 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_find()
1690 pe->index = tid; in mvpp2_prs_vlan_find()
1692 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_vlan_find()
1693 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid)); in mvpp2_prs_vlan_find()
1698 ri_bits = mvpp2_prs_sram_ri_get(pe); in mvpp2_prs_vlan_find()
1702 ai_bits = mvpp2_prs_tcam_ai_get(pe); in mvpp2_prs_vlan_find()
1711 return pe; in mvpp2_prs_vlan_find()
1713 kfree(pe); in mvpp2_prs_vlan_find()
1722 struct mvpp2_prs_entry *pe; in mvpp2_prs_vlan_add() local
1726 pe = mvpp2_prs_vlan_find(priv, tpid, ai); in mvpp2_prs_vlan_add()
1728 if (!pe) { in mvpp2_prs_vlan_add()
1735 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_vlan_add()
1736 if (!pe) in mvpp2_prs_vlan_add()
1748 pe->index = tid_aux; in mvpp2_prs_vlan_add()
1749 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_vlan_add()
1750 ri_bits = mvpp2_prs_sram_ri_get(pe); in mvpp2_prs_vlan_add()
1761 memset(pe, 0 , sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_vlan_add()
1762 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
1763 pe->index = tid; in mvpp2_prs_vlan_add()
1765 mvpp2_prs_match_etype(pe, 0, tpid); in mvpp2_prs_vlan_add()
1767 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_add()
1769 mvpp2_prs_sram_shift_set(pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_vlan_add()
1772 mvpp2_prs_sram_ai_update(pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
1775 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_vlan_add()
1779 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_TRIPLE, in mvpp2_prs_vlan_add()
1782 mvpp2_prs_tcam_ai_update(pe, ai, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
1784 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
1787 mvpp2_prs_tcam_port_map_set(pe, port_map); in mvpp2_prs_vlan_add()
1789 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_vlan_add()
1792 kfree(pe); in mvpp2_prs_vlan_add()
1815 struct mvpp2_prs_entry *pe; in mvpp2_prs_double_vlan_find() local
1818 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_double_vlan_find()
1819 if (!pe) in mvpp2_prs_double_vlan_find()
1821 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_find()
1833 pe->index = tid; in mvpp2_prs_double_vlan_find()
1834 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_double_vlan_find()
1836 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid1)) in mvpp2_prs_double_vlan_find()
1837 && mvpp2_prs_tcam_data_cmp(pe, 4, swab16(tpid2)); in mvpp2_prs_double_vlan_find()
1842 ri_mask = mvpp2_prs_sram_ri_get(pe) & MVPP2_PRS_RI_VLAN_MASK; in mvpp2_prs_double_vlan_find()
1844 return pe; in mvpp2_prs_double_vlan_find()
1846 kfree(pe); in mvpp2_prs_double_vlan_find()
1856 struct mvpp2_prs_entry *pe; in mvpp2_prs_double_vlan_add() local
1859 pe = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2); in mvpp2_prs_double_vlan_add()
1861 if (!pe) { in mvpp2_prs_double_vlan_add()
1868 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_double_vlan_add()
1869 if (!pe) in mvpp2_prs_double_vlan_add()
1888 pe->index = tid_aux; in mvpp2_prs_double_vlan_add()
1889 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_double_vlan_add()
1890 ri_bits = mvpp2_prs_sram_ri_get(pe); in mvpp2_prs_double_vlan_add()
1902 memset(pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_double_vlan_add()
1903 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
1904 pe->index = tid; in mvpp2_prs_double_vlan_add()
1908 mvpp2_prs_match_etype(pe, 0, tpid1); in mvpp2_prs_double_vlan_add()
1909 mvpp2_prs_match_etype(pe, 4, tpid2); in mvpp2_prs_double_vlan_add()
1911 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
1913 mvpp2_prs_sram_shift_set(pe, 2 * MVPP2_VLAN_TAG_LEN, in mvpp2_prs_double_vlan_add()
1915 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_double_vlan_add()
1917 mvpp2_prs_sram_ai_update(pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_double_vlan_add()
1920 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
1924 mvpp2_prs_tcam_port_map_set(pe, port_map); in mvpp2_prs_double_vlan_add()
1925 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_double_vlan_add()
1928 kfree(pe); in mvpp2_prs_double_vlan_add()
1936 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_proto() local
1949 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_proto()
1950 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1951 pe.index = tid; in mvpp2_prs_ip4_proto()
1954 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1955 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_proto()
1957 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_proto()
1960 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_proto()
1962 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_MASK, in mvpp2_prs_ip4_proto()
1965 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
1966 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_proto()
1968 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_proto()
1971 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1972 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
1980 pe.index = tid; in mvpp2_prs_ip4_proto()
1982 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_ip4_proto()
1983 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_ip4_proto()
1984 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip4_proto()
1986 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L); in mvpp2_prs_ip4_proto()
1987 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
1990 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
1991 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
1999 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_cast() local
2007 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_cast()
2008 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
2009 pe.index = tid; in mvpp2_prs_ip4_cast()
2013 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, in mvpp2_prs_ip4_cast()
2015 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip4_cast()
2020 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); in mvpp2_prs_ip4_cast()
2021 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); in mvpp2_prs_ip4_cast()
2022 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); in mvpp2_prs_ip4_cast()
2023 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); in mvpp2_prs_ip4_cast()
2024 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, in mvpp2_prs_ip4_cast()
2032 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_cast()
2033 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_cast()
2035 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_cast()
2038 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_cast()
2041 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
2042 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_cast()
2051 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_proto() local
2063 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_proto()
2064 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
2065 pe.index = tid; in mvpp2_prs_ip6_proto()
2068 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_proto()
2069 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_proto()
2070 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip6_proto()
2071 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_proto()
2075 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip6_proto()
2076 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_proto()
2079 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_proto()
2082 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
2083 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_proto()
2091 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_cast() local
2102 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_cast()
2103 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
2104 pe.index = tid; in mvpp2_prs_ip6_cast()
2107 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
2108 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip6_cast()
2110 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_cast()
2113 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_cast()
2115 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, in mvpp2_prs_ip6_cast()
2117 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_cast()
2119 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_cast()
2122 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
2123 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_cast()
2158 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow_init() local
2162 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_def_flow_init()
2163 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
2164 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
2167 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_def_flow_init()
2170 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
2171 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow_init()
2174 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
2175 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_def_flow_init()
2182 struct mvpp2_prs_entry pe; in mvpp2_prs_mh_init() local
2184 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mh_init()
2186 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
2187 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
2188 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
2190 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mh_init()
2193 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mh_init()
2196 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
2197 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
2205 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_init() local
2207 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_init()
2210 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
2211 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
2213 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_init()
2215 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_init()
2216 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_init()
2219 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mac_init()
2222 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
2223 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_init()
2235 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_init() local
2268 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_dsa_init()
2269 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_init()
2270 pe.index = MVPP2_PE_DSA_DEFAULT; in mvpp2_prs_dsa_init()
2271 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_init()
2274 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_dsa_init()
2275 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_dsa_init()
2278 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_dsa_init()
2281 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_dsa_init()
2283 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_init()
2289 struct mvpp2_prs_entry pe; in mvpp2_prs_etype_init() local
2298 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2299 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2300 pe.index = tid; in mvpp2_prs_etype_init()
2302 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); in mvpp2_prs_etype_init()
2304 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, in mvpp2_prs_etype_init()
2306 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_etype_init()
2307 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2311 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2312 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2313 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2314 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2316 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2324 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2325 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2326 pe.index = tid; in mvpp2_prs_etype_init()
2328 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); in mvpp2_prs_etype_init()
2331 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2332 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2333 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2336 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2341 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2342 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2343 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2344 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2346 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2354 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2355 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2356 pe.index = tid; in mvpp2_prs_etype_init()
2358 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); in mvpp2_prs_etype_init()
2361 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2362 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2363 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2368 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2373 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2374 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2375 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2376 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2380 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2388 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2389 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2390 pe.index = tid; in mvpp2_prs_etype_init()
2392 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); in mvpp2_prs_etype_init()
2393 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2398 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_etype_init()
2399 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2402 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_etype_init()
2405 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2410 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2411 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2412 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2413 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2415 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2423 pe.index = tid; in mvpp2_prs_etype_init()
2426 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2427 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2429 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2434 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_etype_init()
2435 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_etype_init()
2436 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2440 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2441 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2442 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2443 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2445 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2453 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2454 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2455 pe.index = tid; in mvpp2_prs_etype_init()
2457 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); in mvpp2_prs_etype_init()
2460 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_etype_init()
2463 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_etype_init()
2464 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2467 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2471 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2472 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2473 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2474 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2476 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2479 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2480 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2481 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
2484 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_etype_init()
2487 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2488 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2489 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2492 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2497 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2498 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2499 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2500 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2502 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2516 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_init() local
2550 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_vlan_init()
2551 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2552 pe.index = MVPP2_PE_VLAN_DBL; in mvpp2_prs_vlan_init()
2554 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
2556 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_init()
2557 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_vlan_init()
2560 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_vlan_init()
2563 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
2566 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2567 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
2570 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_vlan_init()
2571 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2572 pe.index = MVPP2_PE_VLAN_NONE; in mvpp2_prs_vlan_init()
2574 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
2575 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_vlan_init()
2579 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
2582 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
2583 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
2591 struct mvpp2_prs_entry pe; in mvpp2_prs_pppoe_init() local
2600 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_pppoe_init()
2601 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2602 pe.index = tid; in mvpp2_prs_pppoe_init()
2604 mvpp2_prs_match_etype(&pe, 0, PPP_IP); in mvpp2_prs_pppoe_init()
2606 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_pppoe_init()
2607 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_pppoe_init()
2610 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
2613 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
2618 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2619 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2627 pe.index = tid; in mvpp2_prs_pppoe_init()
2629 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_pppoe_init()
2635 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_pppoe_init()
2636 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_pppoe_init()
2637 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_pppoe_init()
2641 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2642 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2650 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_pppoe_init()
2651 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2652 pe.index = tid; in mvpp2_prs_pppoe_init()
2654 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); in mvpp2_prs_pppoe_init()
2656 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_pppoe_init()
2657 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_pppoe_init()
2660 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
2663 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
2668 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2669 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2677 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_pppoe_init()
2678 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2679 pe.index = tid; in mvpp2_prs_pppoe_init()
2681 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_pppoe_init()
2685 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_pppoe_init()
2686 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_pppoe_init()
2688 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
2693 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
2694 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
2702 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_init() local
2735 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_init()
2736 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2737 pe.index = MVPP2_PE_IP4_PROTO_UN; in mvpp2_prs_ip4_init()
2740 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2741 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_init()
2743 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_init()
2746 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
2748 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip4_init()
2751 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_init()
2753 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
2756 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2757 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
2760 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip4_init()
2761 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2762 pe.index = MVPP2_PE_IP4_ADDR_UN; in mvpp2_prs_ip4_init()
2765 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_init()
2766 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_init()
2767 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip4_init()
2770 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
2773 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
2776 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
2777 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
2785 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_init() local
2828 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2829 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2830 pe.index = tid; in mvpp2_prs_ip6_init()
2833 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
2834 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
2835 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | in mvpp2_prs_ip6_init()
2840 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); in mvpp2_prs_ip6_init()
2841 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2845 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
2846 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2849 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2850 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2851 pe.index = MVPP2_PE_IP6_PROTO_UN; in mvpp2_prs_ip6_init()
2854 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
2855 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
2856 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
2859 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_init()
2863 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2866 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
2869 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
2870 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2873 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2874 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2875 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; in mvpp2_prs_ip6_init()
2878 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
2879 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
2880 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
2883 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2886 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
2889 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
2890 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2893 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
2894 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2895 pe.index = MVPP2_PE_IP6_ADDR_UN; in mvpp2_prs_ip6_init()
2898 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2899 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip6_init()
2901 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
2904 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_init()
2906 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_init()
2908 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
2911 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
2912 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
2984 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, in mvpp2_prs_mac_range_equals() argument
2991 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
3007 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_range_find() local
3010 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_range_find()
3011 if (!pe) in mvpp2_prs_mac_da_range_find()
3013 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_range_find()
3025 pe->index = tid; in mvpp2_prs_mac_da_range_find()
3026 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_mac_da_range_find()
3027 entry_pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_range_find()
3029 if (mvpp2_prs_mac_range_equals(pe, da, mask) && in mvpp2_prs_mac_da_range_find()
3031 return pe; in mvpp2_prs_mac_da_range_find()
3033 kfree(pe); in mvpp2_prs_mac_da_range_find()
3042 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_accept() local
3048 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
3052 if (!pe) { in mvpp2_prs_mac_da_accept()
3072 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_accept()
3073 if (!pe) in mvpp2_prs_mac_da_accept()
3075 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
3076 pe->index = tid; in mvpp2_prs_mac_da_accept()
3079 mvpp2_prs_tcam_port_map_set(pe, 0); in mvpp2_prs_mac_da_accept()
3083 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
3086 pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_accept()
3089 kfree(pe); in mvpp2_prs_mac_da_accept()
3092 mvpp2_prs_hw_inv(priv, pe->index); in mvpp2_prs_mac_da_accept()
3093 priv->prs_shadow[pe->index].valid = false; in mvpp2_prs_mac_da_accept()
3094 kfree(pe); in mvpp2_prs_mac_da_accept()
3099 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_da_accept()
3104 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff); in mvpp2_prs_mac_da_accept()
3114 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
3116 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
3120 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN, in mvpp2_prs_mac_da_accept()
3124 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
3125 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
3126 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_mac_da_accept()
3128 kfree(pe); in mvpp2_prs_mac_da_accept()
3158 struct mvpp2_prs_entry pe; in mvpp2_prs_mcast_del_all() local
3171 pe.index = tid; in mvpp2_prs_mcast_del_all()
3172 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mcast_del_all()
3176 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], in mvpp2_prs_mcast_del_all()
3238 struct mvpp2_prs_entry *pe; in mvpp2_prs_def_flow() local
3241 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
3244 if (!pe) { in mvpp2_prs_def_flow()
3252 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_def_flow()
3253 if (!pe) in mvpp2_prs_def_flow()
3256 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
3257 pe->index = tid; in mvpp2_prs_def_flow()
3260 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
3261 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow()
3264 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
3267 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
3268 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
3269 kfree(pe); in mvpp2_prs_def_flow()