Lines Matching refs:d1
303 movel SICR, %d1 // D1 = clock settings in SICR
304 andl clocking_mask(%d0), %d1
307 orl clocking_txfromrx(%d0), %d1
311 orl clocking_ext(%d0), %d1
313 movel %d1, SICR // update clock settings in SICR
319 movel first_buffer(%d0), %d1 // D1 = starting buffer address
328 movel %d1, (%a1)+ // buffer address
329 addl #BUFFER_LENGTH, %d1
334 movel %d1, (%a1)+ // buffer address
340 movel %d1, (%a1)+ // buffer address
341 addl #BUFFER_LENGTH, %d1
345 movel %d1, (%a1)+ // buffer address
354 movel tx_first_bd(%d0), %d1
355 movew %d1, SCC_TBASE(%a1) // D1 = offset of first TxBD
356 addl #TX_BUFFERS * 8, %d1
357 movew %d1, SCC_RBASE(%a1) // D1 = offset of first RxBD
419 movel %d0, %d1
420 lsll #4, %d1 // D1 bits 7 and 6 = port
421 orl #1, %d1
422 movew %d1, CR // Init SCC RX and TX params
442 movel ch_status_addr(%d0), %d1
443 clrl STATUS_OPEN(%d1) // confirm the port is closed
453 movel tx_out(%d0), %d1
454 movel %d1, %d2 // D1 = D2 = tx_out BD# = desc#
463 lsll #3, %d1 // BD is 8-bytes long
464 addl tx_first_bd(%d0), %d1 // D1 = current tx_out BD addr
466 movel 4(%d1), %a1 // A1 = dest address
468 movew %d2, 2(%d1) // length into BD
470 bsetl #31, (%d1) // CP go ahead
473 movel tx_out(%d0), %d1
474 addl #1, %d1
475 cmpl #TX_BUFFERS, %d1
477 clrl %d1
478 tx_1: movel %d1, tx_out(%d0)
489 rx: movel rx_in(%d0), %d1 // D1 = rx_in BD#
490 lsll #3, %d1 // BD is 8-bytes long
491 addl rx_first_bd(%d0), %d1 // D1 = current rx_in BD address
492 movew (%d1), %d2 // D2 = RX BD flags
507 movew 2(%d1), %d3
520 movel 4(%d1), %a0 // A0 = source address
538 andw #0xF000, (%d1) // clear CM and error bits
539 bsetl #31, (%d1) // free BD
541 movel rx_in(%d0), %d1
542 addl #1, %d1
543 cmpl #RX_BUFFERS, %d1
545 clrl %d1
546 rx_2: movel %d1, rx_in(%d0)
568 movel tx_in(%d0), %d1
569 movel %d1, %d2 // D1 = D2 = tx_in BD# = desc#
570 lsll #3, %d1 // BD is 8-bytes long
571 addl tx_first_bd(%d0), %d1 // D1 = current tx_in BD address
572 movew (%d1), %d3 // D3 = TX BD flags
579 movel tx_in(%d0), %d1
580 addl #1, %d1
581 cmpl #TX_BUFFERS, %d1
583 clrl %d1
585 movel %d1, tx_in(%d0)
688 movel %d1, -(%sp)
697 movew (%a0), %d1 // D1 = CSR input bits
698 andl #0xE7, %d1 // PM and cable sense bits (no DCE bit)
699 cmpw #STATUS_CABLE_V35 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
701 movew #0x0E08, %d1
705 cmpw #STATUS_CABLE_X21 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
707 movew #0x0408, %d1
711 cmpw #STATUS_CABLE_V24 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
713 movew #0x0208, %d1
717 cmpw #STATUS_CABLE_EIA530 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
719 movew #0x0D08, %d1
723 movew #0x0008, %d1 // D1 = disable everything
730 orw %d2, %d1 // D1 = all requested output bits
734 cmpw old_csr_output(%d0), %d1
736 movew %d1, old_csr_output(%d0)
737 movew %d1, (%a0) // Write CSR output bits
740 movew (PCDAT), %d1
741 andw dcd_mask(%d0), %d1
743 movew (%a0), %d1 // D1 = CSR input bits
744 andw #~STATUS_CABLE_DCD, %d1 // DCD off
748 movew (%a0), %d1 // D1 = CSR input bits
749 orw #STATUS_CABLE_DCD, %d1 // DCD on
751 andw %d2, %d1 // input mask
753 cmpl STATUS_CABLE(%a1), %d1 // check for change
755 movel %d1, STATUS_CABLE(%a1) // update status
767 movel (%sp)+, %d1
782 movel #0x12345678, %d1 // D1 = test value
783 movel %d1, (128 * 1024 - 4)
790 cmpl (%a0), %d1
797 eorl #0xFFFFFFFF, %d1
798 movel %d1, (128 * 1024 - 4)
799 cmpl (%a0), %d1
806 movel %d0, %d1 // D1 = DBf counter
809 dbfw %d1, ram_test_fill
810 subl #0x10000, %d1
811 cmpl #0xFFFFFFFF, %d1