618 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)  in ath10k_pci_write32()  function
672 	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);  in ath10k_pci_soc_write32()
682 	ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);  in ath10k_pci_reg_write32()
703 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,  in ath10k_pci_disable_and_clear_legacy_irq()
705 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,  in ath10k_pci_disable_and_clear_legacy_irq()
716 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_enable_legacy_irq()
1501 		ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_msi_fw_mask()
1523 		ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_msi_fw_unmask()
1859 	ath10k_pci_write32(ar, addr, val);  in ath10k_pci_wake_target_cpu()
2127 	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);  in ath10k_pci_fw_crashed_clear()
2154 	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);  in ath10k_pci_warm_reset_cpu()
2158 	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,  in ath10k_pci_warm_reset_cpu()
2169 	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,  in ath10k_pci_warm_reset_ce()
2172 	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,  in ath10k_pci_warm_reset_ce()
2182 	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +  in ath10k_pci_warm_reset_clear_lf()
2507 	.write32		= ath10k_pci_write32,
2774 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,  in ath10k_pci_init_irq()
2782 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,  in ath10k_pci_deinit_irq_legacy()