291 		ath5k_hw_reg_write(ah,  in ath5k_hw_set_tx_retry_limits()
304 		ath5k_hw_reg_write(ah,  in ath5k_hw_set_tx_retry_limits()
342 	ath5k_hw_reg_write(ah,  in ath5k_hw_reset_tx_queue()
369 		ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,  in ath5k_hw_reset_tx_queue()
385 		ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,  in ath5k_hw_reset_tx_queue()
391 		ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,  in ath5k_hw_reset_tx_queue()
403 		ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,  in ath5k_hw_reset_tx_queue()
408 		ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,  in ath5k_hw_reset_tx_queue()
436 		ath5k_hw_reg_write(ah, ((tq->tqi_ready_time -  in ath5k_hw_reset_tx_queue()
504 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,  in ath5k_hw_reset_tx_queue()
510 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,  in ath5k_hw_reset_tx_queue()
522 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,  in ath5k_hw_reset_tx_queue()
528 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,  in ath5k_hw_reset_tx_queue()
532 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,  in ath5k_hw_reset_tx_queue()
538 		ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);  in ath5k_hw_reset_tx_queue()
637 		ath5k_hw_reg_write(ah, slot_time_clock, AR5K_SLOT_TIME);  in ath5k_hw_set_ifs_intervals()
652 		ath5k_hw_reg_write(ah, (difs_clock <<  in ath5k_hw_set_ifs_intervals()
657 		ath5k_hw_reg_write(ah, pifs_clock | eifs_clock |  in ath5k_hw_set_ifs_intervals()
665 	ath5k_hw_reg_write(ah, slot_time_clock, AR5K_DCU_GBL_IFS_SLOT);  in ath5k_hw_set_ifs_intervals()
668 	ath5k_hw_reg_write(ah, eifs_clock, AR5K_DCU_GBL_IFS_EIFS);  in ath5k_hw_set_ifs_intervals()
676 	ath5k_hw_reg_write(ah, sifs_clock, AR5K_DCU_GBL_IFS_SIFS);  in ath5k_hw_set_ifs_intervals()