406 static u32 carl9170_def_val(u32 reg, bool is_2ghz, bool is_40mhz)  in carl9170_def_val()  argument
414 			if (is_40mhz)  in carl9170_def_val()
419 			if (is_40mhz)  in carl9170_def_val()
433 				bool is_2ghz, bool is_40mhz)  in carl9170_init_phy_from_eeprom()  argument
458 	if (!is_40mhz) {  in carl9170_init_phy_from_eeprom()
460 				     is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
466 	val = carl9170_def_val(AR9170_PHY_REG_DESIRED_SZ, is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
472 	val = carl9170_def_val(AR9170_PHY_REG_RF_CTL4, is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
480 	val = carl9170_def_val(AR9170_PHY_REG_RF_CTL3, is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
485 	val = carl9170_def_val(0x1c8864, is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
490 	val = carl9170_def_val(AR9170_PHY_REG_RXGAIN, is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
496 			       is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
501 	val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ, is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
510 			       is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
516 			       is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
523 			       is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
529 	val = carl9170_def_val(AR9170_PHY_REG_TPCRG1, is_2ghz, is_40mhz);  in carl9170_init_phy_from_eeprom()
548 	bool is_40mhz = conf_is_ht40(&ar->hw->conf);  in carl9170_init_phy()  local
553 		if (is_40mhz) {  in carl9170_init_phy()
573 	err = carl9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);  in carl9170_init_phy()