197 	else if (rfpath == RF90_PATH_B)  in _rtl88e_phy_rf_serial_read()
808 	case RF90_PATH_B:  in rtl88e_phy_config_rf_with_headerfile()
853 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in _rtl88e_phy_init_bb_rf_register_definition()
858 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in _rtl88e_phy_init_bb_rf_register_definition()
863 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in _rtl88e_phy_init_bb_rf_register_definition()
866 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in _rtl88e_phy_init_bb_rf_register_definition()
870 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in _rtl88e_phy_init_bb_rf_register_definition()
874 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in _rtl88e_phy_init_bb_rf_register_definition()
879 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl88e_phy_init_bb_rf_register_definition()
884 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;  in _rtl88e_phy_init_bb_rf_register_definition()
887 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in _rtl88e_phy_init_bb_rf_register_definition()
891 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl =  in _rtl88e_phy_init_bb_rf_register_definition()
899 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;  in _rtl88e_phy_init_bb_rf_register_definition()
904 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;  in _rtl88e_phy_init_bb_rf_register_definition()
909 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
914 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;  in _rtl88e_phy_init_bb_rf_register_definition()
919 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
924 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;  in _rtl88e_phy_init_bb_rf_register_definition()
927 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in _rtl88e_phy_init_bb_rf_register_definition()
930 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;  in _rtl88e_phy_init_bb_rf_register_definition()
1000 		} else if (rf_path == RF90_PATH_B) {  in _rtl88e_get_txpower_index()
1001 			cckpowerlevel[RF90_PATH_B] =  in _rtl88e_get_txpower_index()
1002 			  rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];  in _rtl88e_get_txpower_index()
1003 			bw20powerlevel[RF90_PATH_B] =  in _rtl88e_get_txpower_index()
1004 			  rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] +  in _rtl88e_get_txpower_index()
1005 			  rtlefuse->txpwr_ht20diff[RF90_PATH_B][index];  in _rtl88e_get_txpower_index()
1006 			ofdmpowerlevel[RF90_PATH_B] =  in _rtl88e_get_txpower_index()
1007 			  rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] +  in _rtl88e_get_txpower_index()
1008 			  rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][index];  in _rtl88e_get_txpower_index()
1009 			bw40powerlevel[RF90_PATH_B] =  in _rtl88e_get_txpower_index()
1010 			  rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];  in _rtl88e_get_txpower_index()
1880 			rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,  in _rtl88e_phy_lc_calibrate()
1887 			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,  in _rtl88e_phy_lc_calibrate()
1901 			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,  in _rtl88e_phy_lc_calibrate()