Lines Matching refs:rtlphy
272 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_rf_serial_read() local
273 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92d_phy_rf_serial_read()
320 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_rf_serial_write() local
321 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92d_phy_rf_serial_write()
356 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_set_rf_reg() local
366 if (rtlphy->rf_mode != RF_OP_BY_FW) { in rtl92d_phy_set_rf_reg()
411 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_init_bb_rf_register_definition() local
415 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl92d_phy_init_bb_rf_register_definition()
417 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl92d_phy_init_bb_rf_register_definition()
419 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92d_phy_init_bb_rf_register_definition()
422 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92d_phy_init_bb_rf_register_definition()
425 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl92d_phy_init_bb_rf_register_definition()
427 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl92d_phy_init_bb_rf_register_definition()
429 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92d_phy_init_bb_rf_register_definition()
431 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92d_phy_init_bb_rf_register_definition()
435 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; in _rtl92d_phy_init_bb_rf_register_definition()
437 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; in _rtl92d_phy_init_bb_rf_register_definition()
441 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; in _rtl92d_phy_init_bb_rf_register_definition()
443 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; in _rtl92d_phy_init_bb_rf_register_definition()
447 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = in _rtl92d_phy_init_bb_rf_register_definition()
449 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = in _rtl92d_phy_init_bb_rf_register_definition()
454 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl92d_phy_init_bb_rf_register_definition()
455 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl92d_phy_init_bb_rf_register_definition()
456 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92d_phy_init_bb_rf_register_definition()
457 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92d_phy_init_bb_rf_register_definition()
461 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92d_phy_init_bb_rf_register_definition()
463 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92d_phy_init_bb_rf_register_definition()
465 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92d_phy_init_bb_rf_register_definition()
467 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92d_phy_init_bb_rf_register_definition()
471 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; in _rtl92d_phy_init_bb_rf_register_definition()
473 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; in _rtl92d_phy_init_bb_rf_register_definition()
477 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; in _rtl92d_phy_init_bb_rf_register_definition()
479 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; in _rtl92d_phy_init_bb_rf_register_definition()
483 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; in _rtl92d_phy_init_bb_rf_register_definition()
484 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; in _rtl92d_phy_init_bb_rf_register_definition()
485 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92d_phy_init_bb_rf_register_definition()
486 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92d_phy_init_bb_rf_register_definition()
489 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; in _rtl92d_phy_init_bb_rf_register_definition()
490 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; in _rtl92d_phy_init_bb_rf_register_definition()
491 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; in _rtl92d_phy_init_bb_rf_register_definition()
492 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in _rtl92d_phy_init_bb_rf_register_definition()
495 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; in _rtl92d_phy_init_bb_rf_register_definition()
496 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; in _rtl92d_phy_init_bb_rf_register_definition()
497 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; in _rtl92d_phy_init_bb_rf_register_definition()
498 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in _rtl92d_phy_init_bb_rf_register_definition()
501 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; in _rtl92d_phy_init_bb_rf_register_definition()
502 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; in _rtl92d_phy_init_bb_rf_register_definition()
503 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; in _rtl92d_phy_init_bb_rf_register_definition()
504 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; in _rtl92d_phy_init_bb_rf_register_definition()
507 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; in _rtl92d_phy_init_bb_rf_register_definition()
508 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; in _rtl92d_phy_init_bb_rf_register_definition()
509 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; in _rtl92d_phy_init_bb_rf_register_definition()
510 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in _rtl92d_phy_init_bb_rf_register_definition()
513 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE; in _rtl92d_phy_init_bb_rf_register_definition()
514 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE; in _rtl92d_phy_init_bb_rf_register_definition()
515 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE; in _rtl92d_phy_init_bb_rf_register_definition()
516 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE; in _rtl92d_phy_init_bb_rf_register_definition()
519 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE; in _rtl92d_phy_init_bb_rf_register_definition()
520 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE; in _rtl92d_phy_init_bb_rf_register_definition()
521 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE; in _rtl92d_phy_init_bb_rf_register_definition()
522 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE; in _rtl92d_phy_init_bb_rf_register_definition()
525 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; in _rtl92d_phy_init_bb_rf_register_definition()
526 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; in _rtl92d_phy_init_bb_rf_register_definition()
527 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; in _rtl92d_phy_init_bb_rf_register_definition()
528 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; in _rtl92d_phy_init_bb_rf_register_definition()
531 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; in _rtl92d_phy_init_bb_rf_register_definition()
532 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; in _rtl92d_phy_init_bb_rf_register_definition()
640 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_store_pwrindex_diffrate_offset() local
678 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; in _rtl92d_store_pwrindex_diffrate_offset()
681 rtlphy->pwrgroup_cnt, index, in _rtl92d_store_pwrindex_diffrate_offset()
682 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); in _rtl92d_store_pwrindex_diffrate_offset()
684 rtlphy->pwrgroup_cnt++; in _rtl92d_store_pwrindex_diffrate_offset()
715 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_bb_config() local
733 rtlphy->pwrgroup_cnt = 0; in _rtl92d_phy_bb_config()
747 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, in _rtl92d_phy_bb_config()
853 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_get_hw_reg_originalvalue() local
855 rtlphy->default_initialgain[0] = in rtl92d_phy_get_hw_reg_originalvalue()
857 rtlphy->default_initialgain[1] = in rtl92d_phy_get_hw_reg_originalvalue()
859 rtlphy->default_initialgain[2] = in rtl92d_phy_get_hw_reg_originalvalue()
861 rtlphy->default_initialgain[3] = in rtl92d_phy_get_hw_reg_originalvalue()
865 rtlphy->default_initialgain[0], in rtl92d_phy_get_hw_reg_originalvalue()
866 rtlphy->default_initialgain[1], in rtl92d_phy_get_hw_reg_originalvalue()
867 rtlphy->default_initialgain[2], in rtl92d_phy_get_hw_reg_originalvalue()
868 rtlphy->default_initialgain[3]); in rtl92d_phy_get_hw_reg_originalvalue()
869 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, in rtl92d_phy_get_hw_reg_originalvalue()
871 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, in rtl92d_phy_get_hw_reg_originalvalue()
875 ROFDM0_RXDETECTOR3, rtlphy->framesync); in rtl92d_phy_get_hw_reg_originalvalue()
882 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_get_txpower_index() local
900 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { in _rtl92d_get_txpower_index()
906 } else if (rtlphy->rf_type == RF_2T2R) { in _rtl92d_get_txpower_index()
919 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_ccxpower_index_check() local
921 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl92d_ccxpower_index_check()
922 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl92d_ccxpower_index_check()
971 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_set_bw_mode() local
978 if (rtlphy->set_bwmode_inprogress) in rtl92d_phy_set_bw_mode()
985 rtlphy->set_bwmode_inprogress = true; in rtl92d_phy_set_bw_mode()
987 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? in rtl92d_phy_set_bw_mode()
991 switch (rtlphy->current_chan_bw) { in rtl92d_phy_set_bw_mode()
1006 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); in rtl92d_phy_set_bw_mode()
1009 switch (rtlphy->current_chan_bw) { in rtl92d_phy_set_bw_mode()
1038 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); in rtl92d_phy_set_bw_mode()
1042 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); in rtl92d_phy_set_bw_mode()
1043 rtlphy->set_bwmode_inprogress = false; in rtl92d_phy_set_bw_mode()
1172 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_enable_rf_env() local
1173 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92d_phy_enable_rf_env()
1208 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_restore_rf_env() local
1209 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92d_phy_restore_rf_env()
1230 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_switch_rf_setting() local
1312 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; in _rtl92d_phy_switch_rf_setting()
1494 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_patha_iqk_5g_normal() local
1566 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_patha_iqk_5g_normal()
1568 rtlphy->iqk_bb_backup[1]); in _rtl92d_phy_patha_iqk_5g_normal()
1616 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_pathb_iqk_5g_normal() local
1684 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_pathb_iqk_5g_normal()
1686 rtlphy->iqk_bb_backup[2]); in _rtl92d_phy_pathb_iqk_5g_normal()
1796 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_iq_calibrate() local
1827 rtlphy->adda_backup, IQK_ADDA_REG_NUM); in _rtl92d_phy_iq_calibrate()
1829 rtlphy->iqk_mac_backup); in _rtl92d_phy_iq_calibrate()
1831 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM); in _rtl92d_phy_iq_calibrate()
1835 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, in _rtl92d_phy_iq_calibrate()
1839 if (!rtlphy->rfpi_enable) in _rtl92d_phy_iq_calibrate()
1855 rtlphy->iqk_mac_backup); in _rtl92d_phy_iq_calibrate()
1932 if (!rtlphy->rfpi_enable) in _rtl92d_phy_iq_calibrate()
1936 rtlphy->adda_backup, IQK_ADDA_REG_NUM); in _rtl92d_phy_iq_calibrate()
1939 rtlphy->iqk_mac_backup); in _rtl92d_phy_iq_calibrate()
1942 rtlphy->iqk_bb_backup, in _rtl92d_phy_iq_calibrate()
1946 rtlphy->iqk_bb_backup, in _rtl92d_phy_iq_calibrate()
1959 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_iq_calibrate_5g_normal() local
1993 rtlphy->adda_backup, in _rtl92d_phy_iq_calibrate_5g_normal()
1996 rtlphy->iqk_mac_backup); in _rtl92d_phy_iq_calibrate_5g_normal()
1999 rtlphy->iqk_bb_backup, in _rtl92d_phy_iq_calibrate_5g_normal()
2003 rtlphy->iqk_bb_backup, in _rtl92d_phy_iq_calibrate_5g_normal()
2009 rtlphy->iqk_mac_backup); in _rtl92d_phy_iq_calibrate_5g_normal()
2011 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, in _rtl92d_phy_iq_calibrate_5g_normal()
2014 if (!rtlphy->rfpi_enable) in _rtl92d_phy_iq_calibrate_5g_normal()
2089 rtlphy->iqk_bb_backup, in _rtl92d_phy_iq_calibrate_5g_normal()
2093 rtlphy->iqk_bb_backup, in _rtl92d_phy_iq_calibrate_5g_normal()
2097 rtlphy->iqk_mac_backup); in _rtl92d_phy_iq_calibrate_5g_normal()
2099 if (!rtlphy->rfpi_enable) in _rtl92d_phy_iq_calibrate_5g_normal()
2103 rtlphy->adda_backup, in _rtl92d_phy_iq_calibrate_5g_normal()
2282 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_iq_calibrate() local
2293 "IQK:Start!!!channel %d\n", rtlphy->current_channel); in rtl92d_phy_iq_calibrate()
2364 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; in rtl92d_phy_iq_calibrate()
2365 rtlphy->reg_e9c = rege9c = result[final_candidate][1]; in rtl92d_phy_iq_calibrate()
2368 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4]; in rtl92d_phy_iq_calibrate()
2369 rtlphy->reg_ebc = regebc = result[final_candidate][5]; in rtl92d_phy_iq_calibrate()
2380 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ in rtl92d_phy_iq_calibrate()
2381 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ in rtl92d_phy_iq_calibrate()
2393 rtlphy->current_channel); in rtl92d_phy_iq_calibrate()
2396 rtlphy->iqk_matrix[indexforchannel]. in rtl92d_phy_iq_calibrate()
2398 rtlphy->iqk_matrix[indexforchannel].iqk_done = in rtl92d_phy_iq_calibrate()
2409 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_reload_iqk_setting() local
2418 rtlphy->iqk_matrix[indexforchannel].iqk_done); in rtl92d_phy_reload_iqk_setting()
2419 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && in rtl92d_phy_reload_iqk_setting()
2420 rtlphy->need_iqk) { in rtl92d_phy_reload_iqk_setting()
2433 if ((rtlphy->iqk_matrix[indexforchannel]. in rtl92d_phy_reload_iqk_setting()
2437 rtlphy->iqk_matrix[ in rtl92d_phy_reload_iqk_setting()
2439 (rtlphy->iqk_matrix[ in rtl92d_phy_reload_iqk_setting()
2442 if ((rtlphy->iqk_matrix[ in rtl92d_phy_reload_iqk_setting()
2447 rtlphy->iqk_matrix[ in rtl92d_phy_reload_iqk_setting()
2449 (rtlphy->iqk_matrix[ in rtl92d_phy_reload_iqk_setting()
2455 rtlphy->need_iqk = false; in rtl92d_phy_reload_iqk_setting()
2690 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_lc_calibrate() local
2699 rtlphy->lck_inprogress = true; in rtl92d_phy_lc_calibrate()
2709 rtlphy->lck_inprogress = false; in rtl92d_phy_lc_calibrate()
2742 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_reset_iqk_result() local
2747 (int)(sizeof(rtlphy->iqk_matrix) / in rtl92d_phy_reset_iqk_result()
2752 rtlphy->iqk_matrix[i].value[0][0] = 0x100; in rtl92d_phy_reset_iqk_result()
2753 rtlphy->iqk_matrix[i].value[0][2] = 0x100; in rtl92d_phy_reset_iqk_result()
2754 rtlphy->iqk_matrix[i].value[0][4] = 0x100; in rtl92d_phy_reset_iqk_result()
2755 rtlphy->iqk_matrix[i].value[0][6] = 0x100; in rtl92d_phy_reset_iqk_result()
2756 rtlphy->iqk_matrix[i].value[0][1] = 0x0; in rtl92d_phy_reset_iqk_result()
2757 rtlphy->iqk_matrix[i].value[0][3] = 0x0; in rtl92d_phy_reset_iqk_result()
2758 rtlphy->iqk_matrix[i].value[0][5] = 0x0; in rtl92d_phy_reset_iqk_result()
2759 rtlphy->iqk_matrix[i].value[0][7] = 0x0; in rtl92d_phy_reset_iqk_result()
2760 rtlphy->iqk_matrix[i].iqk_done = false; in rtl92d_phy_reset_iqk_result()
2769 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92d_phy_sw_chnl_step_by_step() local
2778 u8 num_total_rfpath = rtlphy->num_total_rfpath; in _rtl92d_phy_sw_chnl_step_by_step()
2836 rtlphy->rfreg_chnlval[rfpath] = in _rtl92d_phy_sw_chnl_step_by_step()
2837 ((rtlphy->rfreg_chnlval[rfpath] & in _rtl92d_phy_sw_chnl_step_by_step()
2842 rtlphy->rfreg_chnlval[rfpath] = in _rtl92d_phy_sw_chnl_step_by_step()
2843 rtlphy->rfreg_chnlval in _rtl92d_phy_sw_chnl_step_by_step()
2846 rtlphy->rfreg_chnlval[rfpath] = in _rtl92d_phy_sw_chnl_step_by_step()
2847 rtlphy->rfreg_chnlval in _rtl92d_phy_sw_chnl_step_by_step()
2849 rtlphy->rfreg_chnlval[rfpath] |= in _rtl92d_phy_sw_chnl_step_by_step()
2852 rtlphy->rfreg_chnlval[rfpath] &= in _rtl92d_phy_sw_chnl_step_by_step()
2858 rtlphy->rfreg_chnlval[rfpath]); in _rtl92d_phy_sw_chnl_step_by_step()
2881 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_sw_chnl() local
2885 u8 channel = rtlphy->current_channel; in rtl92d_phy_sw_chnl()
2888 if (rtlphy->sw_chnl_inprogress) in rtl92d_phy_sw_chnl()
2890 if (rtlphy->set_bwmode_inprogress) in rtl92d_phy_sw_chnl()
2898 while (rtlphy->lck_inprogress && timecount < timeout) { in rtl92d_phy_sw_chnl()
2906 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2908 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2931 rtlphy->sw_chnl_inprogress = true; in rtl92d_phy_sw_chnl()
2934 rtlphy->sw_chnl_stage = 0; in rtl92d_phy_sw_chnl()
2935 rtlphy->sw_chnl_step = 0; in rtl92d_phy_sw_chnl()
2937 "switch to channel%d\n", rtlphy->current_channel); in rtl92d_phy_sw_chnl()
2940 if (!rtlphy->sw_chnl_inprogress) in rtl92d_phy_sw_chnl()
2943 rtlphy->current_channel, in rtl92d_phy_sw_chnl()
2944 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) { in rtl92d_phy_sw_chnl()
2950 rtlphy->sw_chnl_inprogress = false; in rtl92d_phy_sw_chnl()
2955 rtlphy->sw_chnl_inprogress = false; in rtl92d_phy_sw_chnl()
2963 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_set_io() local
2967 rtlphy->current_io_type, rtlphy->set_io_inprogress); in rtl92d_phy_set_io()
2968 switch (rtlphy->current_io_type) { in rtl92d_phy_set_io()
2970 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; in rtl92d_phy_set_io()
2972 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); in rtl92d_phy_set_io()
2975 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; in rtl92d_phy_set_io()
2984 rtlphy->set_io_inprogress = false; in rtl92d_phy_set_io()
2986 rtlphy->current_io_type); in rtl92d_phy_set_io()
2992 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_set_io_cmd() local
2997 iotype, rtlphy->set_io_inprogress); in rtl92d_phy_set_io_cmd()
3016 if (postprocessing && !rtlphy->set_io_inprogress) { in rtl92d_phy_set_io_cmd()
3017 rtlphy->set_io_inprogress = true; in rtl92d_phy_set_io_cmd()
3018 rtlphy->current_io_type = iotype; in rtl92d_phy_set_io_cmd()
3238 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_phy_config_macphymode_info() local
3242 rtlphy->rf_type = RF_2T2R; in rtl92d_phy_config_macphymode_info()
3249 rtlphy->rf_type = RF_2T2R; in rtl92d_phy_config_macphymode_info()
3256 rtlphy->rf_type = RF_1T1R; in rtl92d_phy_config_macphymode_info()
3392 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_update_bbrf_configuration() local
3515 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; in rtl92d_update_bbrf_configuration()
3533 if (rtlphy->rf_type == RF_1T1R) { in rtl92d_update_bbrf_configuration()
3562 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; in rtl92d_update_bbrf_configuration()
3564 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, in rtl92d_update_bbrf_configuration()
3566 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, in rtl92d_update_bbrf_configuration()
3571 rtlphy->rfreg_chnlval[i]); in rtl92d_update_bbrf_configuration()