77 #define rtc1_write(offset, value)	writew((value), rtc1_base + (offset))  macro
115 	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));  in write_elapsed_second()
116 	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));  in write_elapsed_second()
117 	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));  in write_elapsed_second()
127 	rtc1_write(ECMPLREG, 0);  in vr41xx_rtc_release()
128 	rtc1_write(ECMPMREG, 0);  in vr41xx_rtc_release()
129 	rtc1_write(ECMPHREG, 0);  in vr41xx_rtc_release()
130 	rtc1_write(RTCL1LREG, 0);  in vr41xx_rtc_release()
131 	rtc1_write(RTCL1HREG, 0);  in vr41xx_rtc_release()
196 	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));  in vr41xx_rtc_set_alarm()
197 	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));  in vr41xx_rtc_set_alarm()
198 	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));  in vr41xx_rtc_set_alarm()
266 	rtc1_write(RTCL1LREG, count);  in rtclong1_interrupt()
267 	rtc1_write(RTCL1HREG, count >> 16);  in rtclong1_interrupt()
324 	rtc1_write(ECMPLREG, 0);  in rtc_probe()
325 	rtc1_write(ECMPMREG, 0);  in rtc_probe()
326 	rtc1_write(ECMPHREG, 0);  in rtc_probe()
327 	rtc1_write(RTCL1LREG, 0);  in rtc_probe()
328 	rtc1_write(RTCL1HREG, 0);  in rtc_probe()