Lines Matching refs:BIT1
495 #define IO_PIN BIT1
514 #define RXSTATUS_OVERRUN BIT1
552 #define TXSTATUS_UNDERRUN BIT1
572 #define MISCSTATUS_BRG1_ZERO BIT1
598 #define SICR_BRG1_ZERO BIT1
632 #define TXSTATUS_UNDERRUN BIT1
637 #define DICR_RECEIVE BIT1
1598 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 ); in mgsl_isr_receive_dma()
5240 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5303 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
5444 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); in usc_process_rxoverrun_sync()
5533 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); in usc_start_receiver()
6119 if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1)) in usc_loopback_frame()
6329 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_async_clock()
7282 while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { in mgsl_dma_test()
7297 if ( status & (BIT5 | BIT1) ) in mgsl_dma_test()
7323 if ( status & (BIT8 | BIT3 | BIT1) ) { in mgsl_dma_test()