Lines Matching refs:BIT5
491 #define RECEIVE_STATUS BIT5
507 #define RXSTATUS_BREAK_RECEIVED BIT5
508 #define RXSTATUS_ABORT_RECEIVED BIT5
547 #define TXSTATUS_ABORT_SENT BIT5
568 #define MISCSTATUS_CTS_LATCHED BIT5
593 #define SICR_CTS_ACTIVE BIT5
595 #define SICR_CTS (BIT5|BIT4)
628 #define TXSTATUS_ABORT_SENT BIT5
5918 RegValue |= BIT5; in usc_set_async_mode()
5975 RegValue |= BIT5; in usc_set_async_mode()
7188 if ( !(status & BIT4) && (status & BIT5) ) { in mgsl_dma_test()
7282 while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { in mgsl_dma_test()
7297 if ( status & (BIT5 | BIT1) ) in mgsl_dma_test()